Datasheet

Input/Output (I/O) Ports
Port D
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Input/Output (I/O) Ports 393
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 18-5 summarizes the operation of the port D pins.
Table 18-5. Port D Pin Functions
DDRD
Bit
PTD Bit I/O Pin Mode
Accesses to DDRD Accesses to PTD
Read/Write Read Write
0X
(1)
Notes:
1. X = don’t care.
Input, Hi-Z
(2)
2. Hi-Z = high impedance.
DDRD[7:0] Pin PTD[7:0]
(3)
3. Writing affects data register, but does not affect input.
1 X Output DDRD[7:0] PTD[7:0] PTD[7:0]