Datasheet

Low-Voltage Inhibit (LVI)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
422 Low-Voltage Inhibit (LVI) Freescale Semiconductor
22.4 Functional Description
Figure 22-2 shows the structure of the LVI module.
Figure 22-2. LVI Module Block Diagram
The LVI is enabled out of reset. The LVI module contains a bandgap
reference circuit and comparator. Clearing the LVI power disable bit,
LVIPWRD, enables the LVI to monitor V
DD
voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset
when V
DD
falls below a voltage, V
TRIPF
. Setting the LVI enable in stop
mode bit, LVISTOP, enables the LVI to operate in stop mode.
Addr.Register Name Bit 7654321Bit 0
$FE0F
Low-Voltage Inhibit Status
Register
(LVISR)
Read: LVIOUT
LVIIE
LVIIF00000
Write:
LVIIACK
Reset:00000000
= Unimplemented
Figure 22-1. LVI I/O Register Summary
LOW V
DD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVI RESET
V
DD
> V
TRIPR
= 0
V
DD
≤ V
TRIPF
= 1
FROM CONFIG1
FROM CONFIG1
V
DD
FROM CONFIG1
LVISEL[1:0]
FROM CONFIG2
TO LVISR
LVISTOP
LVIRSTD
INTERRUPT
REQUEST
LVI
LVIOUT
TO LVISR
EDGE
DETECT
LATCH
CLR
FROM LVISR
LVIIE
LVIIF
FROM LVISR
LVIIACK
DEFAULT
ENABLED