Datasheet
Electrical Specifications
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
440 Electrical Specifications Freescale Semiconductor
24.8 5V Control Timing
Capacitance
Ports (as input or output)
C
OUT
C
IN
—
—
—
—
12
8
pF
POR re-arm voltage
(7)
V
POR
0—100mV
POR rise-time ramp rate
(8)
R
POR
0.02 — — V/ms
Monitor mode entry voltage (at IRQ
pin)
V
HI
1.5 ×
V
DD
—8V
Pullup resistors
(9)
PTA0–PTA3 and PTD4–PTD7 as KBI0–KBI7
RST
, IRQ
R
PU1
R
PU2
21
21
30
30
39
39
kΩ
kΩ
Low-voltage inhibit, trip falling voltage
V
TRIPF
2.1 — 2.8 V
Low-voltage inhibit, trip rising voltage
V
TRIPR
2.2 — 2.9 V
Notes:
1. V
DD
= 3.0 to 3.6 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I
DD
.
4. Wait I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
.
5. The 8kHz clock is from a 32kHz external square wave clock input at OSC1, for the driving the RTC. Due to loading effects,
the I
DD
values will be larger when a 32kHz crystal circuit is connected.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
9. R
PU1
and
R
PU2
are measured at
V
DD
= 3.3V.
Table 24-6. 5V Control Timing
Characteristic
(1)
Notes:
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Symbol Min Max Unit
Internal operating frequency
(2)
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
f
OP
—8MHz
RST
input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
750 — ns
Table 24-5. 3.3V DC Electrical Characteristics
Characteristic
(1)
Symbol Min Typ
(2)
Max Unit