Datasheet

Memory Map
Input/Output (I/O) Section
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 63
$FE00
SIM Break Status Register
(SBSR)
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
$FE02 Reserved
Read:
RRRRRRRR
Write:
Reset:
$FE03
SIM Break Flag Control
Register
(SBFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
Read: 0000IF18IF17IF16IF15
Write:RRRRRRRR
Reset:00000000
$FE07 Reserved
Read:
RRRRRRRR
Write:
Reset:
$FE08
FLASH Control Register
(FLCR)
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
U = Unaffected X = Indeterminate
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 13)