Datasheet

Configuration Registers (CONFIG)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
82 Configuration Registers (CONFIG) Freescale Semiconductor
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK
cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE: When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 ICLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the
MCU is not protected from a low power condition. However, when using
the short stop recovery configuration option, the 32 ICLK delay is less
than the LVI’s turn-on time and there exists a period in start-up where the
LVI is not protecting the MCU.
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 21. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
5.5 Configuration Register 2 (CONFIG2)
The CONFIG2 register can be written once after each reset.
Address: $001D
Bit 7654321Bit 0
Read:
PEE
STOP_
IRCDIS
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
Write:
Reset:0000000
††
1
††
†† Reset by POR only.
Figure 5-3. Configuration Register 2 (CONFIG2)