Datasheet

MC68HC908QYA/QTA Family Data Sheet, Rev. 3
192 Freescale Semiconductor
• The ADC that is on the QYxA can operate while the MCU is in stop mode allowing lower power
operation. This also adds a lower noise environment for precise ADC results.
• Enabling an ADC channel no longer overrides the digital I/O function of the associated pin. To
prevent the digital I/O from interfering with the ADC read of the pin, the data direction bit associated
with the port pin must be set as input.
• Finally, the new ADC can be configured to select two different reference clock sources:
– The internal bus x 4
– An internal asynchronous source
The internal asynchronous clock source allows the ADC to be clocked for operation in stop mode.
A.2.1.1 Registers Affected
The ADCHx bits can be used to select additional ADC channels or bandgap measurement.
10-bit ADC uses the new ADRH register for the upper 2 bits.
A long sample time option has been added to conserve power at the expense of longer conversion times.
This option is selected using the new ADLSMP bit in the ADCLK register. (The bit location was previously
reserved.)
The ADC will now run in stop mode if the ACLKEN bit is set to enable the asynchronous clock inside the
ADC module. Utilizing stop mode for an ADC conversion gives the quietest operating mode to get
extremely accurate ADC readings. (This bit location now used by ACLKEN was reserved — it always read
as a 0 and writes to that location had no affect.)
Bit 7654321Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
= Unimplemented
Figure A-1. ADC10 Status and Control Register (ADSCR)
Bit 7654321Bit 0
Read:000000AD9AD8
Write:
Reset:00000000
= Unimplemented
Figure A-2. ADC10 Data Register High (ADRH), 10-Bit Mode
Bit 7654321Bit 0
Read:
ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN
Write:
Reset:00000000
Figure A-3. ADC10 Clock Register (ADCLK)