Datasheet

Analog-to-Digital Converter (ADC10) Module
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
48 Freescale Semiconductor
3.8.3 ADC10 Result Low Register (ADRL)
This register holds the LSBs of the result. This register is updated each time a conversion completes.
Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result
registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH.
3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
ADLPC — ADC10 Low-Power Configuration Bit
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
Bit 7654321Bit 0
Read:00000000
Write:
Reset:00000000
= Unimplemented
Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode
Bit 7654321Bit 0
Read:000000AD9AD8
Write:
Reset:00000000
= Unimplemented
Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset:00000000
= Unimplemented
Figure 3-6. ADC10 Data Register Low (ADRL)
Bit 7654321Bit 0
Read:
ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN
Write:
Reset:00000000
Figure 3-7. ADC10 Clock Register (ADCLK)