MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data HC12 Microcontrollers MC68HC912D60A/D Rev. 3.1 08/2005 freescale.
MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data — Rev. 3.1 Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Technical Data 4 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A List of Paragraphs List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23 Section 2. Central Processing Unit . . . . .
List of Paragraphs Section 17. MSCAN Controller . . . . . . . . . . . . . . . . . . . . 303 Section 18. Analog-to-Digital Converter . . . . . . . . . . . . 349 Section 19. Development Support. . . . . . . . . . . . . . . . . 377 Section 20. Electrical Specifications. . . . . . . . . . . . . . . 405 Section 21. Appendix: CGM Practical Aspects . . . . . . 427 Section 22. Appendix: Changes from MC68HC912D60437 Section 23. Appendix: Information on MC68HC912D60A Mask Set Changes . . . . . . . . . . . . . . . . .
Technical Data — MC68HC912D60A Table of Contents Technical Data — List of Paragraphs Technical Data — Table of Contents Technical Data — List of Figures Technical Data — List of Tables Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . . 24 1.
Table of Contents Section 3. Pinout and Signal Descriptions 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 MC68HC912D60A Pin Assignments in 112-pin QFP . . . . . . . . 38 3.3 MC68HC912D60A Pin Assignments in 80-pin QFP . . . . . . . . . 40 3.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.
Table of Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5 Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7 Operation . . . . . .
Table of Contents 9.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.7 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.8 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.9 Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Section 10. I/O Ports with Key Wake-up 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.3 MC68HC912D60A Oscillator Specification. . . . . . . . . . . . . . . 176 12.4 MC68HC912D60C Colpitts Oscillator Specification . . . . . . . . 179 12.5 MC68HC912D60P Pierce Oscillator Specification . . . . . . . . . 194 Section 13. Pulse Width Modulator 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.2 Introduction . . . .
Table of Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.3 Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.4 Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.5 Message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.6 Interfacing to MI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.
Table of Contents 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 18.5 ATD Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 18.6 ATD Operation In Different MCU Modes . . . . . . . . . . . . . . . . 355 18.7 General Purpose Digital Input Port Operation . . . . . . . . . . . . 357 18.8 Application Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .358 18.9 ATD Registers . . . . . . . . . . . . . . . . . . .
Table of Contents 22.2 Significant changes from the MC68HC912D60 (non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Section 23. Appendix: Information on MC68HC912D60A Mask Set Changes 23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.3 Flash Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Data — MC68HC912D60A List of Figures Figure 1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 3-6 5-1 6-1 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 12-1 12-2 12-3 12-4 13-1 13-2 13-3 14-1 14-2 Title MC68HC912D60A 112-pin QFP Block Diagram . . . . . . . . . . . 29 MC68HC912D60A 80-pin QFP Block Diagram . . . . . . . . . . . . 30 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin Assignments in 112-pin TQFP for MC68HC912D60A . . . .
List of Figures 14-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . . 227 14-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . 228 14-5 Block Diagram for Port7 with Output compare / Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .229 15-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .
List of Figures 20-8 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . . 421 20-9 SPI Timing Diagram (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 423 20-10 SPI Timing Diagram (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 424 MC68HC912D60A — Rev. 3.
List of Figures Technical Data 18 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A List of Tables Table 1-1 1-2 2-1 2-2 3-1 3-2 3-3 3-4 4-1 5-1 5-2 5-3 5-4 8-1 8-2 8-3 8-4 9-1 9-2 11-1 11-2 11-3 11-4 11-5 13-1 13-2 13-3 14-1 14-2 Title Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Development Tools Ordering Information. . . . . . . . . . . . . . . . . 28 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . . 34 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .
List of Tables 14-3 15-1 15-2 15-3 15-4 16-1 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 Loop Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 SS Output Selection . . . . . . . . . . . . . .
List of Tables 19-12 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 21-1 Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 408 Supply Current . . . . . . . . .
List of Tables Technical Data 22 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . . 24 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 Block Diagrams. . . . . . . . . . . . . . . . .
General Description 1.3 Devices Covered in this Document The MC68HC912D60C and MC68HC912D60P are devices similar to the MC68HC912D60A, but with different oscillator configurations. Refer to Section 12. Oscillator for more details. The generic term MC68HC912D60A is used throughout this document to mean all derivatives mentioned above, except in Section 12. Oscillator, where it refers only to the MC68HC912D60A device. 1.
General Description Features • Analog-to-digital converters – 2 x 8-channels, 10-bit resolution in 112TQFP – 1 x 8-channels, 8-bit resolution in 80QFP • 1M bit per second, CAN 2.
General Description • Serial interfaces – Two asynchronous serial communications interfaces (SCI) – MI-Bus implemented on final devices – Synchronous serial peripheral interface (SPI) • LIM (light integration module) – WCR (windowed COP watchdog, real time interrupt, clock monitor) – ROC (reset and clocks) – MEBI (multiplexed external bus interface) – MBI (internal bus interface and map) – INT (interrupt control) • Clock generation – Phase-locked loop clock frequency multiplier – Limp home mode in abse
General Description Ordering Information 1.5 Ordering Information Table 1-1.
General Description Table 1-2. Development Tools Ordering Information Description Name MCUez Order Number Free from World Wide Web Serial Debug Interface SDI M68SDIL (3–5V), M68DIL12 (SDIL + MCUez + SDBUG12) Evaluation board EVB M68EVB912D60 (EVB only) M68KIT912D60 (EVB + SDIL12) NOTE: SDBUG12 is a P & E Micro Product. It can be obtained from P & E from their web site (http://www.pemicro.com) for approximately $100. Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.
General Description Block Diagrams 1.
General Description PLL Enhanced capture timer PW0 PW1 PW2 PW3 PWM PORT S PORT P PORT E XIRQ IRQ R/W LSTRB/TAGLO ECLK MODA/IPIPE0 MODB/IPIPE1/CGMTST DBE/CAL/ECLK SISO/MISO MOMI/MOSI SCK SS PORT CAN SCI1 SPI PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 RxD1 TxD1 DDRS SCI0 (MI BUS) RxD0 TxD0 Lite integration module (LIM) EXTAL XTAL RESET IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 DDRP XFC VDDPLL VSSPLL AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 DDRCAN BKGD Periodic interrupt COP watchdog Clock monitor Bre
Technical Data — MC68HC912D60A Section 2. Central Processing Unit 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 Indexed Addressing Modes . . . . . . .
Central Processing Unit 7 A 0 7 B 0 8-BIT ACCUMULATORS A & B OR 15 D 0 16-BIT DOUBLE ACCUMULATOR D 15 IX 0 INDEX REGISTER X 15 IY 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER S X H I N Z V C CONDITION CODE REGISTER Figure 2-1. Programming Model Accumulators A and B are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations.
Central Processing Unit Data Types Condition Code Register (CCR) contains five status indicators, two interrupt masking bits, and a STOP disable bit. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a previous operation. After a reset, the CPU fetches a vector from the appropriate address and begins executing instructions.
Central Processing Unit Table 2-1.
Central Processing Unit Indexed Addressing Modes 2.6 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The postbyte and extensions do the following tasks: • Specify which index register is used. • Determine whether a value in an accumulator is used as an offset.
Central Processing Unit 2.7 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the opcode map.
Technical Data — MC68HC912D60A Section 3. Pinout and Signal Descriptions 3.1 Contents 3.2 MC68HC912D60A Pin Assignments in 112-pin QFP . . . . . . . . 38 3.3 MC68HC912D60A Pin Assignments in 80-pin QFP . . . . . . . . . 40 3.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinout and Signal Descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MC68HC912D60A 112TQFP 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 PAD17/AN17 PAD07/AN07 PAD16/AN16 PAD06/AN06 PAD15/AN15 PAD05/AN05 PAD14/AN14 PAD04/AN04 PAD13/AN13 PAD03/AN03 PAD12/AN12 PAD02/AN02 PAD11/AN11 PAD01/AN01 PAD10/AN10 PAD00/AN00 VRL0 VRH0 VSS VDD PA7/ADDR15/DATA15/DATA7 PA6/ADDR14/DATA14/DATA6 PA5/ADDR13/DATA13/DATA5 PA4/ADDR12/DATA12/DATA4 PA3/AD
Pinout and Signal Descriptions MC68HC912D60A Pin Assignments in 112-pin QFP 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 AA J V1 57 29 F D 56 0.13 N M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 S1 A S C2 VIEW AB θ2 0.050 C 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3.
Pinout and Signal Descriptions 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP3/PW3 PP4 PP5 PP6 PP7 VDDX VSSX PCAN0/RxCAN PCAN1/TxCAN TEST PS7/SS PS6/SCK PS5/SDO/MOSI PS4/SDI/MISO PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 VSSAD VDDAD 3.
Pinout and Signal Descriptions MC68HC912D60A Pin Assignments in 80-pin QFP L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 -CH SEATING PLANE N M G U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1.
Pinout and Signal Descriptions 3.4 Power Supply Pins MC68HC912D60A power and ground pins are described below and summarized in Table 3-1. All power supply pins must be connected to appropriate supplies. On no account must any pins be left floating. 3.4.1 Internal Power (VDD) and Ground (VSS) Power is supplied to the MCU through VDD and VSS.
Pinout and Signal Descriptions Power Supply Pins 3.4.5 VDDPLL, VSSPLL Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. NOTE: The VSSPLL pin should always be grounded even if the PLL is not used. The VDDPLL pin should not be left floating. It is recommended to connect the VDDPLL pin to ground if the PLL is not used. 3.4.6 XFC PLL loop filter.
Pinout and Signal Descriptions Table 3-1. MC68HC912D60A Power and Ground Connection Summary Pin Number Mnemonic 80-pin QFP 112-pin QFP VDD 9, 49 12, 65 VSS 10, 50 14, 66 VDDX 30, 75 42, 107 VSSX 29, 74 40, 106 VDDA 61 85 VSSA 62 88 VRH1 — 86 VRL1 — 87 VRH0 51 67 VRL0 52 68 VDDPLL 31 43 VSSPLL 33 45 Description Internal power and ground. External power and ground, supply to pin drivers.
Pinout and Signal Descriptions Signal Descriptions NOTE: When selecting a crystal, it is recommended to use one with the lowest possible frequency in order to minimise EMC emissions. 3.5.1.2 External Oscillator Connections XTAL is the crystal output. The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal.
Pinout and Signal Descriptions output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously. This allows the part to reach a proper reset state even if the clocks have failed, while allowing synchronized operation when starting out of reset.
Pinout and Signal Descriptions Signal Descriptions vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are pending, processing begins by fetching the normal reset vector ($FFFE:FFFF). 3.5.4 Maskable Interrupt Request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or levelsensitive triggering is program selectable (INTCR register).
Pinout and Signal Descriptions 3.5.6 Mode Select (SMODN, MODA, and MODB) The state of these pins during reset determine the MCU operating mode. After reset, MODA and MODB can be configured as instruction queue tracking signals IPIPE0 and IPIPE1. MODA and MODB have active pulldowns during reset. The SMODN pin has an active pull-up when configured as input. This pin can be used as BKGD or TAGHI after reset. 3.5.
Pinout and Signal Descriptions Signal Descriptions 3.5.9 Read/Write (R/W) In all modes this pin can be used as general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. 3.5.10 Low-Byte Strobe (LSTRB) In all modes this pin can be used as general-purpose I/O and is an input with an active pull-up out of reset.
Pinout and Signal Descriptions 3.5.13 Inverted ECLK (ECLK) The ECLK pin (PE7) can be used to latch the address for demultiplexing. It has the same behavior as the ECLK, except is inverted. In expanded modes this pin is used to enable the drive control of external buses during external reads. Use of the ECLK is controlled by the NDBE and DBENE bits in the PEAR register. 3.5.
Pinout and Signal Descriptions Signal Descriptions Table 3-2. MC68HC912D60A Signal Description Summary Pin Name Pin Number Description 80-pin 112-pin ADDR[7:0] DATA[7:0] 23–16 31–24 ADDR[15:8] DATA[15:8] 48–41 64–57 DBE 25 36 Data bus control and, in expanded mode, enables the drive control of external buses during external reads. ECLK 25 36 Inverted ECLK used to latch the address. External bus pins share function with general-purpose I/O ports A and B.
Pinout and Signal Descriptions Table 3-2.
Pinout and Signal Descriptions Port Signals which can be read and written at any time, and, with the exception of port AD0, port AD1 (available only in 112TQFP), PE[1:0], RxCAN and TxCAN, a data direction register which controls the direction of each pin. After reset all general purpose I/O pins are configured as input. 3.6.1 Port A Port A pins are used for address and data in expanded modes. In single chip modes, the pins can be used as I/O.
Pinout and Signal Descriptions When the PUPB bit in the PUCR register is set, all port B input pins are pulled-up internally by an active pull-up device. This bit has no effect if the port is being used in expanded modes as the pull-ups are inactive. Setting the RDPB bit in register RDRIV causes all port B outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. 3.6.
Pinout and Signal Descriptions Port Signals 3.6.4 Port G Port G pins are used for key wake-ups that can be used with the pins configured as inputs or outputs. The key wake-ups are triggered with a falling edge signal (KWPG). An interrupt is generated if the corresponding bit is enabled (KWIEG). If any of the interrupts is not enabled, the corresponding pin can be used as a general purpose I/O pin. Refer to I/O Ports with Key Wake-up.
Pinout and Signal Descriptions configured for output. On reset the DDRH bits are cleared and the corresponding pin is configured for input. Port PHUPD determines what type of resistive load is used for Port H input pins when PUPH bit is set in the PUCR register. When PHUPD pin is low, it loads a pull-down in all Port H input pins. When PHUPD pin is high, it loads a pull-up in all Port H input pins. In 80-pin version, the PHUPD is connected internally to VSS. The PH4 will have a pull-down.
Pinout and Signal Descriptions Port Signals Port AD1 pins are inputs; no data direction register is associated with this port. The port has no resistive input loads and no reduced drive controls. Refer to Analog-to-Digital Converter. Port AD1 is not available in the 80-pin package. 3.6.8 Port AD0 Input to the analog-to-digital subsystem and general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD0[7:0].
Pinout and Signal Descriptions 3.6.10 Port S Port S is the 8-bit interface to the standard serial interface consisting of the two serial communications interfaces (SCI1 and SCI0) and the serial peripheral interface (SPI) subsystems. Port S pins are available for general-purpose parallel I/O when standard serial functions are not enabled. Port S pins serve several functions depending on the various internal control registers.
Pinout and Signal Descriptions Port Signals Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset Refer to Enhanced Capture Timer. Table 3-3.
Pinout and Signal Descriptions 3.6.12 Port Pull-Up Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. Table 3-4 summarizes the port pull-up/pulldown default status and controls. Table 3-4.
Technical Data — MC68HC912D60A Section 4. Registers 4.1 Contents 4.2 Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 Register Block The register block can be mapped to any 2K byte boundary within the standard 64K byte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address. The register block occupies the first 512 bytes of the 2K byte block.
Registers Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA(1) $0001 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB(1) $0002 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA(1) $0003 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB(1) $0004 0 0 0 0 0 0 0 0 Reserved(3) $0005 0 0 0 0 0 0 0 0 Reserved(3) $0006 0 0 0 0 0 0 0 0 Reserved(3) $0007 0 0 0 0 0 0 0 0 Reserved(3) $0008 PE7 PE6 PE5 PE4 PE3 PE2
Registers Register Block Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0021 0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW BRKCT1 $0022 Bit 15 14 13 12 11 10 9 Bit 8 BRKAH $0023 Bit 7 6 5 4 3 2 1 Bit 0 BRKAL $0024 Bit 15 14 13 12 11 10 9 Bit 8 BRKDH $0025 Bit 7 6 5 4 3 2 1 Bit 0 BRKDL $0026 0 0 0 0 0 0 0 0 reserved $0027 0 0 0 0 0 0 0 0 reserved $0028 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PORTG $0029 PH7 PH6 PH5 PH4 PH3 PH2 P
Registers Address Bit 7 6 5 4 3 2 1 Bit 0 Name $004B Bit 7 6 5 4 3 2 1 Bit 0 PWCNT3 $004C Bit 7 6 5 4 3 2 1 Bit 0 PWPER0 $004D Bit 7 6 5 4 3 2 1 Bit 0 PWPER1 $004E Bit 7 6 5 4 3 2 1 Bit 0 PWPER2 $004F Bit 7 6 5 4 3 2 1 Bit 0 PWPER3 $0050 Bit 7 6 5 4 3 2 1 Bit 0 PWDTY0 $0051 Bit 7 6 5 4 3 2 1 Bit 0 PWDTY1 $0052 Bit 7 6 5 4 3 2 1 Bit 0 PWDTY2 $0053 Bit 7 6 5 4 3 2 1 Bit 0 PWDTY3 $0054 0 0 0 PSWAI CENTR R
Registers Register Block Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0072 $0073 Bit 15 14 13 12 11 10 9 Bit 8 ADR01H Bit 7 Bit 6 0 0 0 0 0 0 ADR01L $0074 Bit 15 14 13 12 11 10 9 Bit 8 ADR02H $0075 Bit 7 Bit 6 0 0 0 0 0 0 ADR02L $0076 Bit 15 14 13 12 11 10 9 Bit 8 ADR03H $0077 Bit 7 Bit 6 0 0 0 0 0 0 ADR03L $0078 Bit 15 14 13 12 11 10 9 Bit 8 ADR04H $0079 Bit 7 Bit 6 0 0 0 0 0 0 ADR04L $007A Bit 15 14 13 12 11 10 9 Bi
Registers Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0096 Bit 15 14 13 12 11 10 9 Bit 8 TC3 $0097 Bit 7 6 5 4 3 2 1 Bit 0 TC3 $0098 Bit 15 14 13 12 11 10 9 Bit 8 TC4 $0099 Bit 7 6 5 4 3 2 1 Bit 0 TC4 $009A Bit 15 14 13 12 11 10 9 Bit 8 TC5 $009B Bit 7 6 5 4 3 2 1 Bit 0 TC5 $009C Bit 15 14 13 12 11 10 9 Bit 8 TC6 $009D Bit 7 6 5 4 3 2 1 Bit 0 TC6 $009E Bit 15 14 13 12 11 10 9 Bit 8 TC7 $009F Bit 7 6 5 4 3 2
Registers Register Block Address Bit 7 6 5 4 3 2 1 Bit 0 Name $00BA Bit 15 14 13 12 11 10 9 Bit 8 TC1H $00BB Bit 7 6 5 4 3 2 1 Bit 0 TC1H $00BC Bit 15 14 13 12 11 10 9 Bit 8 TC2H $00BD Bit 7 6 5 4 3 2 1 Bit 0 TC2H $00BE Bit 15 14 13 12 11 10 9 Bit 8 TC3H $00BF Bit 7 6 5 4 3 2 1 Bit 0 TC3H $00C0 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC0BDH $00C1 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SC0BDL $00C2 LOOPS WOMS RS
Registers Address Bit 7 6 5 4 $00EF EEDIV7 EEDIV6 EEDIV5 EEDIV4 NOSHB (5) 3 2 1 Bit 0 Name EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEDIVL DMY EEMCR $00F0 NOBDML $00F1 SHPROT 1 1 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 EEPROT $00F2 0 0 0 0 0 0 0 0 Reserved $00F3 BULKP 0 AUTO BYTE ROW ERASE EELAT EEPGM EEPROG $00F4 0 0 0 0 0 0 0 LOCK FEE32LCK $00F5 0 0 0 0 0 0 0 BOOTP FEE32MCR $00F6 0 0 0 0 0 0 0 0 Reserved $00F7 0 0 0 FEESWAI HVEN 0
Registers Register Block Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0119 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CIDAR5 $011A AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CIDAR6 $011B AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CIDAR7 $011C AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CIDMR4 $011D AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CIDMR5 $011E AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CIDMR6 $011F AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CIDMR7 $0120– $013C Unimplemented(4) Reserved $013D 0 0
Registers Address Bit 7 6 5 4 3 2 1 Bit 0 Name $01F0 Bit 15 14 13 12 11 10 9 Bit 8 ADR10H $01F1 Bit 7 Bit 6 0 0 0 0 0 0 ADR10L $01F2 Bit 15 14 13 12 11 10 9 Bit 8 ADR11H $01F3 Bit 7 Bit 6 0 0 0 0 0 0 ADR11L $01F4 Bit 15 14 13 12 11 10 9 Bit 8 ADR12H $01F5 Bit 7 Bit 6 0 0 0 0 0 0 ADR12L $01F6 Bit 15 14 13 12 11 10 9 Bit 8 ADR13H $01F7 Bit 7 Bit 6 0 0 0 0 0 0 ADR13L $01F8 Bit 15 14 13 12 11 10 9 Bit 8 ADR14H $
Technical Data — MC68HC912D60A Section 5. Operating Modes and Resource Mapping 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.6 Memory Maps . . . . . . . . . . . . . .
Operating Modes and Resource Mapping The states of the BKGD, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. Table 5-1. Mode Selection BKGD MODB MODA Mode Port A Port B 1 0 0 Normal Single Chip G.P. I/O G.P. I/O 1 0 1 Normal Expanded Narrow ADDR/DATA ADDR 1 1 0 Reserved (Forced to Peripheral) — — 1 1 1 Normal Expanded Wide ADDR/DATA ADDR/DATA 0 0 0 Special Single Chip G.P. I/O G.P.
Operating Modes and Resource Mapping Operating Modes Normal Single-Chip Mode — There are no external address and data buses in this mode. The MCU operates as a standalone device and all program and data resources are on-chip. External port pins normally associated with address and data buses can be used for general-purpose I/O. Normal Expanded Wide Mode — This is a normal mode of operation in which the expanded bus is present with a 16-bit data bus.
Operating Modes and Resource Mapping Special Expanded Narrow Mode — This mode can be used for emulation of normal expanded narrow mode. Ports A and B are used for the16-bit address bus. Port A is used as the data bus, multiplexed with addresses. In this mode, 16-bit data is presented one byte at a time, the high byte followed by the low byte. The address is automatically incremented on the second cycle. Special Peripheral Mode — The CPU is not active in this mode.
Operating Modes and Resource Mapping Background Debug Mode the regular system vectors while BDM is active. While BDM is active, the user memory from $FF00 to $FFFF is not in the map except through serial BDM commands.
Operating Modes and Resource Mapping ESTR — E Clock Stretch Enable Determines if the E Clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. ESTR is always 1 in expanded modes since it is required for address and data bus de-multiplexing and must follow stretched cycles. 0 = E never stretches (always free running). 1 = E stretches high during external access cycles and low during non-visible internal accesses (IVIS=0).
Operating Modes and Resource Mapping Internal Resource Mapping EME — Emulate Port E In single-chip mode PORTE and DDRE are always in the map regardless of the state of this bit. 0 = PORTE and DDRE are in the memory map. 1 = If in an expanded mode, PORTE and DDRE are removed from the internal memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. Normal modes: write once; special modes: write anytime EXCEPT the first time. Read anytime. 5.
Operating Modes and Resource Mapping data. It is made of the 28K byte FEE28 array mapped from $1000 to $7FFF at reset and of the 32 K byte FEE32 array mapped from $8000 to $FFFF at reset. MAPROM bit in the MISC register allows the swapping of the two flash arrays. Table 5-2. Mapping Precedence Precedence Resource 1 BDM ROM (if active) 2 Register Space 3 RAM 4 EEPROM 5 On-Chip Flash EEPROM (MC68HC912D60A) 6 External Memory 5.5.
Operating Modes and Resource Mapping Internal Resource Mapping MMSWAI — Memory Mapping Interface Stop in Wait Control This bit controls access to the memory mapping interface when in Wait mode. Normal modes: write anytime; special modes: write never. Read anytime. 0 = Memory mapping interface continues to function during Wait mode. 1 = Memory mapping interface access is shut down during Wait mode. 5.5.
Operating Modes and Resource Mapping 5.5.3 EEPROM Mapping The MC68HC912D60A has 1K bytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset EEPROM address space begins at location $0C00 but can be mapped to any 4K byte boundary within the standard 64K byte address space.
Operating Modes and Resource Mapping Internal Resource Mapping 5.5.4 Miscellaneous System Control Register Additional mapping and external resource controls are available. To use external resources the part must be operated in one of the expanded modes.
Operating Modes and Resource Mapping RFSTR1, RFSTR0 — Register Following Stretch This two bit field determines the amount of clock stretch on accesses to the 512 byte Register Following Map. It is valid regardless of the state of the NDRF bit. In Single Chip and Peripheral Modes this bit has no meaning or effect. Table 5-3.
Operating Modes and Resource Mapping Memory Maps 5.6 Memory Maps The following diagrams illustrate the memory map for each mode of operation immediately after reset.
Operating Modes and Resource Mapping Technical Data 84 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 6. Bus Control and Input/Output 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 Detecting Access Type from External Signals . . . . . . . . . . . . . 85 6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.
Bus Control and Input/Output that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus. Figure 6-1. Access Type vs.
Bus Control and Input/Output Registers Bit 7 6 5 4 3 2 1 Bit 0 Single Chip PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RESET: — — — — — — — — Expanded & Periph: ADDR15/ DATA15 ADDR14/ DATA14 ADDR13/ DATA13 ADDR12/ DATA12 ADDR11/ DATA11 ADDR10/ DATA10 ADDR9/ DATA9 ADDR8/ DATA8 Expanded narrow ADDR15/ DATA15/ DATA7 ADDR14/ DATA14/ DATA6 ADDR13/ DATA13/ DATA5 ADDR12/ DATA12/ DATA4 ADDR11/ DATA11/ DATA3 ADDR10/ DATA10/ DATA2 ADDR9/ DATA9/ DATA1 ADDR8/ DATA8/ DATA0 PORTA — Port A
Bus Control and Input/Output Bit 7 6 5 4 3 2 1 Bit 0 Single Chip PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 RESET: — — — — — — — — Expanded & Periph: ADDR7/ DATA7 ADDR6/ DATA6 ADDR5/ DATA5 ADDR4/ DATA4 ADDR3/ DATA3 ADDR2/ DATA2 ADDR1/ DATA1 ADDR0/ DATA0 Expanded narrow ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 PORTB — Port B Register $0001 Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0] (except in narrow mode) respectively.
Bus Control and Input/Output Registers BIT 7 6 5 4 3 2 1 BIT 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 RESET: — — — — — — — — Alt.
Bus Control and Input/Output 0 = Associated pin is a high-impedance input 1 = Associated pin is an output PE[1:0] are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be read regardless of whether the alternate interrupt functions are enabled. This register is not in the map in peripheral mode and expanded modes while the EME control bit is set. Read and write anytime.
Bus Control and Input/Output Registers In normal expanded modes, the reset vector is located in external memory. The DBE and ECLK are required for de-multiplexing address and data, but LSTRB and R/W are only needed by the system when there are external writable resources. Therefore in normal expanded modes, only the DBE and ECLK are configured for their alternate bus control functions and the other bits of port E are configured for generalpurpose I/O.
Bus Control and Input/Output PIPOE — Pipe Status Signal Output Enable Normal: write once; Special: write anytime EXCEPT the first time. Read anytime. 0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test output signal from the CGM module). 1 = PE[6:5] are outputs and indicate the state of the instruction queue (only effective in expanded modes). NECLK — No External E Clock Normal single chip: write once; special single chip: write anytime; all other modes: write never. Read anytime.
Bus Control and Input/Output Registers RDWE — Read/Write Enable Normal: write once; Special: write anytime EXCEPT the first time. Read anytime. This bit has no effect in single-chip modes. 0 = PE2 is a general-purpose I/O pin. 1 = PE2 is configured as the R/W pin. In single chip modes, RDWE has no effect and PE2 is a general-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed it should be enabled before any external writes.
Bus Control and Input/Output Bit 7 6 5 4 3 2 1 Bit 0 PUPH PUPG 0 PUPE 0 0 PUPB PUPA 1 1 0 1 0 0 0 0 RESET: PUCR — Pull-Up Control Register $000C These bits select pull-up resistors for any pin in the corresponding port that is currently configured as an input. This register is not in the map in peripheral mode. Read and write anytime. PUPH — Pull-Up or Pull-Down Port H Enable 0 = Port H pull-ups are disabled. 1 = Enable pull-up/down devices for all port H input pins.
Bus Control and Input/Output Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 RDPH RDPG 0 RDPE 0 RDPB RDPA 0 0 0 0 0 0 0 0 RDRIV — Reduced Drive of I/O Lines $000D These bits select reduced drive for the associated port pins. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). The reduced drive function is independent of which function is being used on a particular port.
Bus Control and Input/Output Technical Data 96 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 7. Flash Memory 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5 Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6 Flash EEPROM Registers . . . . . . . . . . . . . . . . . .
Flash Memory 7.3 Overview The Flash EEPROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. The Flash EEPROM module supports bulk erase only. Each Flash EEPROM module has hardware interlocks which protect stored data from accidental corruption.
Flash Memory Flash EEPROM Registers 7.6 Flash EEPROM Registers FEE32LCK/FEE28LCK — Flash EEPROM Lock Control Register RESET: $00F4/$00F8 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 LOCK 0 0 0 0 0 0 0 0 In normal modes the LOCK bit can only be written once after reset.
Flash Memory FEESWAI — Flash EEPROM Stop in Wait Control 0 = Do not halt Flash EEPROM clock when the part is in wait mode. 0 = Halt Flash EEPROM clock when the part is in wait mode. HVEN — High-Voltage Enable This bit enables the charge pump to supply high voltages for program and erase operations in the array. HVEN can only be set if either PGM or ERAS are set and the proper sequence for program or erase is followed.
Flash Memory Programming the Flash EEPROM 7.7.2 Normal Operation The Flash EEPROM allows a byte or aligned word read in one bus cycle. A misaligned word read requires an additional bus cycle. The Flash EEPROM array responds to read operations only. Write operations are ignored. 7.7.3 Program/Erase Operation An unprogrammed Flash EEPROM bit has a logic state of one. A bit must be programmed to change its state from one to zero. Erasing a bit returns it to a logic one.
Flash Memory Use this step-by-step procedure to program a row of Flash memory. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write to any aligned word Flash address within the row address range desired (with any data) to select the row. 3. Wait for a time, tNVS (min. 10µs). 4. Set the HVEN bit. 5. Wait for a time, tPGS (min. 5µs). 6. Write one data word (two bytes) to the next aligned word Flash address to be programmed.
Flash Memory 7.9 Erasing the Flash EEPROM The following sequence demonstrates the recommended procedure for erasing any of the Flash EEPROM array. 1. Set the ERAS bit. 2. Write to any valid aligned word address in the Flash array. The data written and the address written are not important. The boot block will be erased only if the control bit BOOTP is negated. 3. Wait for a time, tNVS (min. 10µs). 4. Set the HVEN bit. 5. Wait for a time, tERAS (8ms). 6. Clear the ERAS bit. 7. Wait for a time, tNVHL (min.
Flash Memory 7.11 Flash protection bit FPOPEN The FPOPEN bit is located in EEMCR – EEPROM Module Configuration Register, bit 4. FPOPEN – Opens the Flash array for program or erase 0 = The whole Flash array (32-Kbyte and 28-Kbyte) is protected. 1 = The whole Flash array (32-Kbyte and 28-Kbyte) is enabled for program or erase FPOPEN can be read at anytime. FPOPEN can be written only to ’0’ for protection but not to ’1’ for unprotect in normal mode. FPOPEN can be written ’0’ and ’1’ in special mode only.
Technical Data — MC68HC912D60A Section 8. EEPROM Memory 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.3 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . . 106 8.4 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .107 8.5 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.
EEPROM Memory program/erase voltage. Programming voltage is derived from the internal VDD supply with an internal charge pump. 8.3 EEPROM Selective Write More Zeros The EEPROM can be programmed such that one or multiple bits are programmed (written to a logic “0”) at a time. However, the user should never program any bit more than once before erasing the entire byte. In other words, the user is not allowed to over write a logic “0” with another “0’.
EEPROM Memory EEPROM Programmer’s Model 8.4 EEPROM Programmer’s Model The EEPROM module consists of two separately addressable sections. The first is an eight-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array itself. At reset, the eight-byte register section starts at address $00EC and the EEPROM array is located from addresses $0C00 to $0FFF. Registers $00EC-$00ED are reserved.
EEPROM Memory A steady internal self-time clock is required to provide accurate counts to meet EEPROM program/erase requirements. This clock is generated via a programmable 10-bit prescaler register. Automatic program/erase termination is also provided. In ordinary situations, with crystal operating properly, the steady internal self-time clock is derived from the input clock source (EXTALi). The divider value is as in EEDIVH:EEDIVL.
EEPROM Memory EEPROM Control Registers EEDIV[9:0] — Prescaler divider Loaded from SHADOW word at reset. Read anytime. Write once in normal modes (SMODN =1) if EELAT = 0 and anytime in special modes (SMODN =0) if EELAT = 0. The prescaler divider is required to produce a self-time clock with a fixed frequency around 28.6 Khz for the range of oscillator frequencies. The divider is set so that the oscillator frequency can be divided by a divide factor that can produce a 35 µs +/- 2µs pulse.
EEPROM Memory EEMCR — EEPROM Module Configuration Bit 7 NOBDML RESET: 6 5 NOSHW (3) — — $00F0 Reserved — 4 (1) (2) FPOPEN — 3 2 1 Bit 0 1 EESWAI PROTLCK DMY 1 1 0 0 1. Bit 5 has a test function and should not be programmed. 2. The FPOPEN bit is available only on the 1L02H and later mask sets. For previous masks, this bit is reserved. 3. Loaded from SHADOW word. Bits[7:4] are loaded at reset from the EEPROM SHADOW word. NOTE: Bit 5 is reserved for test purposes.
EEPROM Memory EEPROM Control Registers FPOPEN — Opens the Flash Block for Program or Erase 0 = The whole Flash array (32-Kbyte and 28-Kbyte) is protected. 1 = The whole Flash array (32-Kbyte and 28-Kbyte) is enable for program or erase. Loaded from SHADOW word at reset. Read anytime. Write anytime in special modes (SMODN=0). Write once ’0’ is allowed in normal mode.
EEPROM Memory EEPROT — EEPROM Block Protect RESET: Bit 7 SHPROT 1 6 1 1 $00F1 5 1 1 4 BPROT4 1 3 BPROT3 1 2 BPROT2 1 1 BPROT1 1 Bit 0 BPROT0 1 Prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. SHPROT — SHADOW Word Protection 0 = The SHADOW word can be programmed and erased. 1 = The SHADOW word is protected from being programmed and erased. BPROT[4:0] — EEPROM Block Protection 0 = Associated EEPROM block can be programmed and erased.
EEPROM Memory EEPROM Control Registers . EEPROG — EEPROM Control RESET: Bit 7 BULKP 1 6 0 0 $00F3 5 AUTO 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 Bit 0 EEPGM 0 BULKP — Bulk Erase Protection 0 = EEPROM can be bulk erased. 1 = EEPROM is protected from being bulk or row erased. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. AUTO — Automatic shutdown of program/erase operation. EEPGM is cleared automatically after the program/erase cycles are finished when AUTO is set.
EEPROM Memory ERASE — Erase Control 0 = EEPROM configuration for programming. 1 = EEPROM configuration for erasure. Read anytime. Write anytime if EEPGM = 0. Configures the EEPROM for erasure or programming. Unless BULKP is set, erasure is by byte, aligned word, row or bulk. EELAT — EEPROM Latch Control 0 = EEPROM set up for normal reads. 1 = EEPROM address and data bus latches set up for programming or erasing. Read anytime. Write anytime except when EEPGM = 1 or EEDIV = 0.
EEPROM Memory Program/Erase Operation 8.6 Program/Erase Operation A program or erase operation should follow the sequence below if AUTO bit is clear: 1. Write BYTE, ROW and ERASE to desired value, write EELAT = 1 2. Write a byte or an aligned word to an EEPROM address 3. Write EEPGM = 1 4. Wait for programming, tPROG or erase, tERASE delay time (10ms) 5. Write EEPGM = 0 6. Write EELAT = 0 If the AUTO bit is set, steps 4 and 5 can be replaced by a step to poll the EEPGM bit until it is cleared.
EEPROM Memory 8.8 Programming EEDIVH and EEDIVL Registers The EEDIVH and EEDIVL registers must be correctly set according to the oscillator frequency before any EEPROM location can be programmed or erased. 8.8.1 Normal mode The EEDIVH and EEDIVL registers are write once in normal mode. Upon system reset, the application program is required to write the correct divider value to EEDIVH and EEDIVL registers based on the oscillator frequency.
EEPROM Memory Programming EEDIVH and EEDIVL Registers EEPROM location at address $0FC0 and $0FC1. Do not program other bits of the high byte of the SHADOW word (location $0FC0); otherwise some regular EEPROM array locations will not be visible. At the next reset, the SHADOW values are loaded into the EEDIVH and EEDIVL registers. They do not require further initialization as long as the oscillator frequency of the target application is not changed. 5.
EEPROM Memory Technical Data 118 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 9. Resets and Interrupts 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.3 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.5 Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . . 123 9.6 Resets. . . . . . . . . . . . . . . . . . . . . . . .
Resets and Interrupts maskable. The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. The priorities of the non-maskable sources are: 1. POR or RESET pin 2. Clock monitor reset 3. COP watchdog reset 4. Unimplemented instruction trap 5. Software interrupt instruction (SWI) 6. XIRQ signal (if X bit in CCR = 0) 9.3 Maskable interrupts Maskable interrupt sources include on-chip peripheral systems and external interrupt service requests.
Resets and Interrupts Latching of Interrupts 9.4 Latching of Interrupts XIRQ is always level triggered and IRQ can be selected as a level triggered interrupt. These level triggered interrupt pins should only be released during the appropriate interrupt service routine. Generally the interrupt service routine will handshake with the interrupting logic to release the pin. In this way, the MCU will start the interrupt service sequence only to determine that there is no longer an interrupt source.
Resets and Interrupts Table 9-1.
Resets and Interrupts Interrupt Control and Priority Registers 9.5 Interrupt Control and Priority Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 IRQE IRQEN DLY 0 0 0 0 0 0 1 1 0 0 0 0 0 INTCR — Interrupt Control Register $001E IRQE — IRQ Select Edge Sensitive Only 0 = IRQ configured for low-level recognition. 1 = IRQ configured to respond only to falling edges (on pin PE1/IRQ). IRQE can be read anytime and written once in normal modes.
Resets and Interrupts Bit 7 6 5 4 3 2 1 Bit 0 1 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 1 1 1 1 0 0 1 0 RESET: HPRIO — Highest Priority I Interrupt $001F Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime. To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO register. For example, writing $F0 to HPRIO would assign highest maskable interrupt priority to the real-time interrupt timer ($FFF0).
Resets and Interrupts Resets 9.6.2 External Reset The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than eight ECLK cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for about 16 ECLK cycles, then released. Eight ECLK cycles later it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred.
Resets and Interrupts 9.7 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states, as follows. 9.7.1 Operating Mode and Memory Map Operating mode and default memory mapping are determined by the states of the BKGD, MODA, and MODB pins during reset. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset.
Resets and Interrupts Register Stacking If the MCU comes out of reset in an expanded mode, port A and port B are used for the address/data bus, and port E pins are normally used to control the external bus (operation of port E pins can be affected by the PEAR register). Out of reset, port G, port H, port P, port S, port T, port CAN[7:2], port AD0 and port AD1 are all configured as general-purpose inputs. 9.7.
Resets and Interrupts required to complete the instruction. Some of the longer instructions can be interrupted and will resume normally after servicing the interrupt. When the CPU begins to service an interrupt, the instruction queue is cleared, the return address is calculated, and then it and the contents of the CPU registers are stacked as shown in Table 9-2. Table 9-2.
Technical Data — MC68HC912D60A Section 10. I/O Ports with Key Wake-up 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . . 130 10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.
I/O Ports with Key Wake-up Pull-up/down status is selected by PGUPD and PHUPD input pins: pullup when PxUPD pin is high, pull-down when PxUPD pin is low. On 80QFP these pins are tied internally so that KWG4 is pull-up and KWH4 is pull-down. Default register addresses, as established after reset, are indicated in the following descriptions. For information on re-mapping the register block, refer to Operating Modes and Resource Mapping. 10.
I/O Ports with Key Wake-up Key Wake-up and Port Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0 0 0 0 0 0 0 0 DDRG — Port G Data Direction Register $002A Data direction register G is associated with port G and designates each pin as an input or output.
I/O Ports with Key Wake-up Bit 7 6 5 4 3 2 1 Bit 0 WI2CE KWIEG6 KWIEG5 KWIEG4 KWIEG3 KWIEG2 KWIEG1 KWIEG0 0 0 0 0 0 0 0 0 RESET: KWIEG — Key Wake-up Port G Interrupt Enable Register $002C Read and write anytime. WI2CE — Wake-up I2C Enable 0 = PG6 default key wake-up on falling edge 1 = I2C Start condition detection on PG7 and PG6 When WI2CE is set, PG6 and PG7 operate in wired-OR or open-drain mode.
I/O Ports with Key Wake-up Key Wake-up and Port Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 KWIFG6 KWIFG5 KWIFG4 KWIFG3 KWIFG2 KWIFG1 KWIFG0 0 0 0 0 0 0 0 0 KWIFG — Key Wake-up Port G Flag Register $002E Each flag, except bit 6, is set by a falling edge on its associated input pin. To clear the flag, write one to the corresponding bit in KWIFG. Read and write anytime Bit 7 always reads zero.
I/O Ports with Key Wake-up Bit 7 6 5 4 3 2 1 Bit 0 KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0 0 0 0 0 0 0 0 0 RESET: KWIFH — Key Wake-up Port H Flag Register $002F Read and write anytime. Each flag is set by a falling edge on its associated input pin. To clear the flag, write one to the corresponding bit in KWIFH.
I/O Ports with Key Wake-up Key Wake-Up Input Filter this time interval is shorter than tKWSP, the majority voting logic may treat the two consecutive pulses as a single valid pulse. The filter is shared by all the KWU pins. Hence any valid triggering level on any KWU pin is seen by the filter. The timing specification applies to the input of the filter. Glitch, filtered out, no STOP wake-up Valid STOP Wake-Up pulse tKWSTP min. tKWSTP max.
I/O Ports with Key Wake-up Technical Data 136 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 11. Clock Functions 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . 141 11.6 Limp-Home and Fast STOP Recovery modes . . . . . . . . .
Clock Functions 11.3 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. The MCU uses several types of internal clock signals derived from the primary clock signal: TxCLK clocks are used by the CPU. ECLK and PCLK are used by the bus interfaces, SPI, PWM, ATD0 and ATD1. MCLK is either PCLK or XCLK, and drives on-chip modules such as SCI0, SCI1 and ECT.
Clock Functions Phase-Locked Loop (PLL) T1CLK T2CLK T3CLK T4CLK INT ECLK PCLK XCLK CANCLK Figure 11-1. Internal Clock Relationships 11.4 Phase-Locked Loop (PLL) The phase-locked loop (PLL) of the MC68HC912D60A is designed for robust operation in an Automotive environment. The allowed PLL crystal or ceramic resonator reference of 0.5 to 8MHz is selected for the wide availability of components with good stability over the automotive temperature range.
Clock Functions EXTAL REDUCED CONSUMPTION OSCILLATOR REFERENCE PROGRAMMABLE DIVIDER LOCK LOCK DETECTOR REFDV <2:0> REFCLK XTAL EXTALi DIVCLK PDET PHASE DETECTOR UP DOWN CPUMP VCO VDDPLL SLOW MODE PROGRAMMABLE CLOCK DIVIDER SLDV <5:0> EXTALi SLWCLK ÷2 LOOP PROGRAMMABLE DIVIDER LOOP FILTER SYN <5:0> XFC PAD ×2 PLLCLK XCLK Figure 11-2. PLL Functional Diagram The PLL may be used to run the MCU from a different time base than the incoming crystal value.
Clock Functions Acquisition and Tracking Modes 11.5 Acquisition and Tracking Modes The lock detector compares the frequencies of the VCO feedback clock, DIVCLK, and the final reference clock, REFCLK. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison.
Clock Functions for the base clock. See Clock Divider Chains. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit is a read-only indicator of the mode of the filter.
Clock Functions Limp-Home and Fast STOP Recovery modes 11.6 Limp-Home and Fast STOP Recovery modes If the crystal frequency is not available due to a crystal failure or a long crystal start-up time, the MCU system clock can be supplied by the VCO at its minimum operating frequency, f VCOMIN. This mode of operation is called Limp-Home Mode and is only available when the VDDPLL supply voltage is at VDD level (i.e. power supply for the PLL module is present).
Clock Functions VCO clock at its minimum frequency, f VCOMIN, is provided as the system clock, allowing the MCU to continue operating. The MCU is said to be operating in “limp-home” mode with the forced VCO clock as the system clock. PLLON and BCSP (‘bus clock select PLL’) signals are forced high and the MCS (‘module clock select’) signal is forced low. The LHOME flag in the PLLFLG register is set to indicate that the MCU is running in limp-home mode.
Clock Functions Limp-Home and Fast STOP Recovery modes values before the clock loss. All clocks return to their normal settings and Clock Monitor control is returned to the CME & FCME bits. If AUTO and BCSP bits were set before the clock loss (selecting the PLL to provide a system clock) the SYSCLK ramps-up and the PLL locks at the previously selected frequency. To prevent PLL operation when the external clock frequency comes back, software should clear the BCSP bit while running in limp-home mode.
Clock Functions Therefore, if the MCU is powered up without an external clock, limphome mode is entered provided the MCU is in a normal mode of operation. VDD Power-On Detector EXTALi (Slow EXTALi) Clock Monitor Fail Limp-Home 13-stage counter (Clocked by XCLK) 0 --> 4096 0 --> 4096 BCSP Reset: BCSP = 0 Internal reset SYSCLK SYSCLK (Slow EXTALi) PLLCLK (L.H.) EXTALi PLLCLK (Software check of Limp-Home Flag) EXTALi Figure 11-4.
Clock Functions Limp-Home and Fast STOP Recovery modes During this power up sequence, after the POR pulse falling edge, the VCO supplies the limp-home clock frequency to the 13-stage counter, as the BCSP output is forced high and MCS is forced low. XCLK, BCLK and MCLK are forced to be PCLK, which is supplied by the VCO at fVCOMIN. The initial period taken for the 13-stage counter to reach 4096 defines the internal reset period.
Clock Functions 11.6.3 STOP Exit and Fast STOP Recovery Stop mode is entered when a STOP instruction is executed. Recovery from STOP depends primarily on the state of the three status bits NOLHM, CME & DLY. The DLY bit controls the duration of the waiting period between the actual exit for some key blocks (e.g. clock monitor, clock generators) and the effective exit from stop for all the rest of the MCU. DLY=1 enables the 13-stage counter to generate a 4096 count delay. DLY=0 selects no delay.
Clock Functions Limp-Home and Fast STOP Recovery modes EXTALi Clock Monitor Fail Limp-Home 0 --> 4096 13-stage counter (Clocked by XCLK) BCSP Restore BCSP STOP (DLY = 1) STOP (DLY = 0) SYSCLK PLLCLK (L.H.) Restore PLLCLK or EXTALi Figure 11-5. STOP Exit and Fast STOP Recovery 11.6.
Clock Functions 11.6.5 Executing the STOP instruction without Limp Home mode, clock monitor enabled (NOLHM=1, CME=1, DLY=X) If the NOLHM bit and the CME (or FCME) bits are set, a clock monitor failure is detected when a STOP instruction is executed and the MCU resets via the clock monitor reset vector. 11.6.6 STOP exit in Limp Home mode with Delay (NOLHM=0, CME=X, DLY=1) If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when a STOP instruction is executed to prevent a clock monitor failure.
Clock Functions Limp-Home and Fast STOP Recovery modes improper EXTALi clock cycles can occur on SYSCLK. This may lead to a code runaway. 11.6.7 STOP exit in Limp Home mode without Delay (Fast Stop Recovery) (NOLHM=0, CME=X, DLY=0) Fast STOP recovery refers to any exit from STOP using DLY=0. If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when a STOP instruction is executed to prevent a clock monitor failure.
Clock Functions Each time the 13-stage counter reaches a count of 4096 XCLK cycles (every 8192 cycles), a check of the clock monitor status is performed. If the clock monitor indicates the presence of an external clock limp-home mode is de-asserted, the LHOME flag is cleared and the limp-home interrupt flag is set. Upon leaving limp-home mode, BCSP and MCS are restored to their values before the loss of clock, and all clocks return to their previous frequencies.
Clock Functions Limp-Home and Fast STOP Recovery modes 11.6.9 Pseudo-STOP exit in Limp Home mode with Delay (NOLHM=0, CME=X, DLY=1) When coming out of Pseudo-STOP mode with the NOLHM bit cleared and the DLY bit set, the MCU goes into limp-home mode (regardless of the state of the CME or FCME bits). The VCO supplies the limp-home clock frequency to the 13-stage counter (XCLK). The BCSP output is forced high and MCS is forced low.
Clock Functions 11.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled (NOLHM=1, CME=1, DLY=X) If the NOLHM bit is set and the CME (or FCME) bits are set, a clock monitor failure is detected when a STOP instruction is executed and the MCU resets via the clock monitor reset vector. 11.6.12 Pseudo-STOP exit without Limp Home mode, clock monitor disabled (NOLHM=1, CME=0, DLY=1) If NOLHM is set to 1 and the CME and FCME bits are cleared, the limp home clock is not used.
Clock Functions Limp-Home and Fast STOP Recovery modes . . Table 11-1. Summary of STOP Mode Exit Conditions Mode Conditions Summary STOP exit without Limp Home mode, clock monitor disabled NOLHM=1 CME=0 DLY=X Oscillator must be stable within 4096 XCLK cycles. XCLK can be modified by SLOW divider register. Use of DLY=0 only recommended with external clock.
Clock Functions 11.6.15 PLL Register Descriptions Bit 7 6 5 4 3 2 1 Bit 0 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 0 0 0 0 RESET: SYNR — Synthesizer Register $0038 Read anytime, write anytime, except when BCSP = 1 (PLL selected as bus clock). If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the bus frequency from the PLL reference frequency by SYNR + 1. Internally, SYSCLK runs at twice the bus frequency.
Clock Functions Limp-Home and Fast STOP Recovery modes RESET: Bit 7 6 5 4 3 2 1 Bit 0 LOCKIF LOCK 0 0 0 0 LHIF LHOME 0 0 0 0 0 0 0 0 PLLFLG — PLL Flags $003B Read anytime, refer to each bit for write conditions. LOCKIF — PLL Lock Interrupt Flag 0 = No change in LOCK bit. 1 = LOCK condition has changed, either from a locked state to an unlocked state or vice versa. To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home mode.
Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM 0 —(1) 1 0 0 0 0 —(2) RESET: PLLCR — PLL Control Register $003C 1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low. 2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low. Read and write anytime. Exceptions are listed below for each bit.
Clock Functions Limp-Home and Fast STOP Recovery modes ACQ — Not in Acquisition If AUTO = 1 (ACQ is Read Only) 0 = PLL VCO is not within the desired tolerance of the target frequency. The loop filter is in high bandwidth, acquisition mode. 1 = After the phase lock loop circuit is turned on, indicates the PLL VCO is within the desired tolerance of the target frequency. The loop filter is in low bandwidth, tracking mode.
Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 0 BCSP BCSS 0 0 MCS 0 0 0 0 0 0 0 0 0 0 RESET: CLKSEL — Clock Generator Clock select Register $003D Read and write anytime. Exceptions are listed below for each bit. BCSP and BCSS bits determine the clock used by the main system including the CPU and buses. BCSP — Bus Clock Select PLL 0 = SYSCLK is derived from the crystal clock or from SLWCLK. 1 = SYSCLK source is the PLL. Cannot be set when PLLON = 0.
Clock Functions Limp-Home and Fast STOP Recovery modes RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0 0 0 0 0 0 0 0 0 SLOW — Slow mode Divider Register $003E Read and write anytime. A write to this register changes the SLWCLK frequency with minimum delay (less than one SLWCLK cycle), thus allowing immediate tuneup of the performance versus power consumption for the modules using this clock.
Clock Functions 11.7 System Clock Frequency formulas See Figure 11-6: SLWCLK = EXTALi / ( 2 x SLOW ) SLOW = 1,2,..
Clock Functions Clock Divider Chains BCSP BCSS 1:x PHASE LOCK LOOP EXTAL SYSCLK PLLCLK ÷2 EXTALi BCSP BCSS 0:0 REDUCED CONSUMPTION OSCILLATOR T CLOCK GENERATOR TCLKs E AND P CLOCK GENERATOR ECLK TO CPU TO BUSES, SPI, PWM, ATD0, ATD1 PCLK EXTALi CLKSRC = 1 BCSP BCSS 0:1 XTAL EXTALi TO MSCAN CLKSRC = 0 MCS = 0 MCLK SLOW MODE CLOCK DIVIDER MCS = 1 SLWCLK ÷2 TO SCI0, SCI1, ECT SYNC XCLK TO RTI, COP TO CAL CLKSW = 0 ÷2 SYNC BDMCLK CLKSW = 1 TO BDM TO CLOCK MONITOR Figure 11-6.
Clock Functions the transition, the clock select output will be held low and all CPU activity will cease until the transition is complete. The Module Clock Select bit MCS determines the clock used by the ECT module and the baud rate generators of the SCIs. In limp-home mode, the output of MCS is forced to 0, but the MCS bit reads the latched value. It allows normal operation of the serial and timer subsystems at a fixed reference frequency while allowing the CPU to operate at a higher, variable frequency.
Clock Functions Clock Divider Chains MCLK REGISTER: TMSK2 BITS: PR2, PR1, PR0 0:0:0 TEN REGISTER: MCCTL BITS: MCPR1, MCPR0 0:0 MCEN ÷2 0:0:1 ÷4 0:1 ÷2 0:1:0 ÷2 1:0 ÷2 0:1:1 ÷2 1:1 MODULUS DOWN COUNTER REGISTER: PACTL BITS: PAEN, CLK1, CLK0 0:x:x 1:0:0 ÷2 1:0:0 Prescaled MCLK 1:0:1 ÷2 1:0:1 1:1:0 ÷2 ÷2 PULSE ACC LOW BYTE 1:1:0 PACLK/256 1:1:1 PACLK/65536 (PAOV) 1:1:1 GATE LOGIC PORT T7 PACLK PAMOD PULSE ACC HIGH BYTE TO TIMER MAIN COUNTER (TCNT) PAEN Figure 11-8.
Clock Functions PCLK 5-BIT MODULUS COUNTER (PR0-PR4) ÷2 ÷2 TO ATD0 and ATD1 ÷2 REGISTER: SP0BR BITS: SPR2, SPR1, SPR0 0:0:0 SPI BIT RATE 0:0:1 MSCAN CLOCK EXTALi ÷2 0:1:0 ÷2 0:1:1 ÷2 1:0:0 ÷2 1:0:1 ÷2 1:1:0 ÷2 1:1:1 CLKSRC SYSCLK ECLK CLKSW BDM BIT CLOCK: BCLK SYNCHRONIZER BKGD IN BKGD DIRECTION BKGD PIN LOGIC BKGD OUT Receive: Detect falling edge, count 12 ECLKs, Sample input Transmit 1: Detect falling edge, count 6 ECLKs while output is high impedance, Drive out 1 E cycle pulse
Clock Functions Real-Time Interrupt In addition, windowed COP operation can be selected. In this mode, writes to the COPRST register must occur in the last 25% of the selected period. A premature write will also reset the part. 11.10 Real-Time Interrupt There is a real time (periodic) interrupt available to the user. This interrupt will occur at one of seven selected rates. An interrupt flag and an interrupt enable bit are associated with this function. There are three bits for the rate select. 11.
Clock Functions 11.12 Clock Function Registers All register addresses shown reflect the reset state. Registers may be mapped to any 2K byte space. Bit 7 6 5 4 3 2 1 Bit 0 RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0 0 0 0 0 0 0 0 0 RESET: RTICTL — Real-Time Interrupt Control Register $0014 RTIE — Real Time Interrupt Enable Read and write anytime. 0 = Interrupt requests from RTI are disabled. 1 = Interrupt will be requested whenever RTIF is set.
Clock Functions Clock Function Registers RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select Read and write anytime. Rate select for real-time interrupt. The clock used for this module is the XCLK. Table 11-4. Real Time Interrupt Rates RTR2 RTR1 RTR0 Divide X By: Time-Out Period Time-Out Period Time-Out Period Time-Out Period X = 125 KHz X = 500 KHz X = 2.0 MHz X = 8.0 MHz OFF OFF OFF OFF 0 0 0 OFF 0 0 1 213 65.536 ms 16.384 ms 4.096 ms 1.024 ms 0 2 14 131.72 ms 32.768 ms 8.196 ms 2.
Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 CME FCME FCMCOP WCOP DISR CR2 CR1 CR0 RESET: 0/1 0 0 0 0 1 1 1 Normal RESET: 0/1 0 0 0 1 1 1 1 Special COPCTL — COP Control Register $0016 CME — Clock Monitor Enable Read and write anytime. If FCME is set, this bit has no meaning nor effect. 0 = Clock monitor is disabled. Slow clocks and stop instruction may be used. 1 = Slow or stopped clocks (including the stop instruction) will cause a clock reset sequence or limp-home mode.
Clock Functions Clock Function Registers FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset Writes are not allowed in normal modes, anytime in special modes. Read anytime. If DISR is set, this bit has no effect. 0 = Normal operation. 1 = A clock monitor failure reset or a COP failure reset is forced depending on the state of CME and if COP is enabled. CME COP enabled Forced reset 0 0 none 0 1 COP failure 1 0 Clock monitor failure 1 1 Both(1) 1.
Clock Functions Table 11-5. COP Watchdog Rates CR2 CR1 CR0 Window COP enabled: Divide X clock by 8.0 MHz X clock. Time-out Window start (1) Window end Effective Window (2) 0 0 0 OFF OFF OFF OFF OFF 0 0 1 2 13 1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms 0 % (3) 0 1 0 2 15 4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 % 0 1 1 2 17 16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.4 % 1 0 0 2 19 65.536 ms -0/+1.024 ms 49.152 ms 64.512 ms 23.4 % 1 0 1 2 21 262.
Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 RESET: COPRST — Arm/Reset COP Timer Register $0017 Always reads $00. Writing $55 to this address is the first step of the COP watchdog sequence. Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may be executed between these writes but both must be completed in the correct order prior to time-out to avoid a watchdog reset.
Clock Functions Technical Data 174 MC68HC912D60A — Rev. 3.
Oscillator Contents Technical Data — MC68HC912D60A Section 12. Oscillator 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.3 MC68HC912D60A Oscillator Specification. . . . . . . . . . . . . . . 176 12.4 MC68HC912D60C Colpitts Oscillator Specification . . . . . . . . 179 12.5 MC68HC912D60P Pierce Oscillator Specification . . . . . . . . . 194 12.2 Introduction The oscillator implementation on the original 0.
Oscillator Level Control circuit to provide a lower power oscillator than traditional Pierce oscillators based on simple inverter circuits. In the following sections, each particular oscillator implementation is described in detail. Refer to the appropriate sections for the mask set being used and optimum external component selection. 12.3 MC68HC912D60A Oscillator Specification This section applies to the 1L02H mask set and all previous MC68HC912D60A versions. 12.3.
Oscillator MC68HC912D60A Oscillator Specification BUF - CFLT 2 OTA + RFLT ALC + BIAS EN RFLT CFLT GM RESD EXTAL XTAL CX-EX Resonator CX-VSS Figure 12-1. MC68HC912D60A Colpitts Oscillator Architecture 12.3.2 MC68HC912D60A Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice.
Oscillator • Minimize Capacitance to VSS on EXTAL pin — The Colpitts oscillator architecture is sensitive to capacitance in parallel with the resonator (from EXTAL to VSS). Follow these techniques: i. Remove ground plane from all layers around resonator and EXTAL route ii. Observe a minimum spacing from the EXTAL trace to all other traces of at least three times the design rule minimum (until the microcontroller’s pin pitch prohibits this guideline) iii.
Oscillator MC68HC912D60C Colpitts Oscillator Specification 12.4 MC68HC912D60C Colpitts Oscillator Specification This section applies to the 2L02H mask set, which refers to the newest set of CGM improvements (to the MC68HC912D60A) with the Colpitts oscillator configuration enabled. The name for these devices is MC68HC912D60C. 12.4.1 MC68HC912D60C Oscillator Design Architecture The Colpitts oscillator architecture is shown in Figure 12-2.
Oscillator BUF - CFLT 2 OTA + RFLT ALC + BIAS EN RFLT CFLT GM RESD EXTAL XTAL CX-EX Resonator CX-VSS Figure 12-2. MC68HC912D60C Colpitts Oscillator Architecture There are the following primary differences between the previous (’A’) and new (’C’) Colpitts oscillator configurations: • Hysteresis was added to the clock input buffer to reduce sensitivity to noise • Internal parasitics were reduced from EXTAL to VSS to increase oscillator gain margin. Technical Data 180 MC68HC912D60A — Rev. 3.
Oscillator MC68HC912D60C Colpitts Oscillator Specification • The bias current to the amplifier was optimized for less variation over process. • The input ESD resistor from EXTAL to the gate of the oscillator amplifier was changed to provide a parallel path, reducing parasitic phase shift in the oscillator. 12.4.1.
Oscillator 12.4.1.2 Internal Parasitic Reduction Any oscillator circuit’s gain margin is reduced when a low AC-impedance (low resistance or high capacitance) is placed in parallel with the resonator. In the Colpitts oscillator configuration, this impedance is dominated by the parasitic capacitance from the EXTAL pin to VSS. Since this capacitance is large compared to the shunt capacitance of the resonator, the gain margin in a Colpitts configuration is less than in other configurations.
Oscillator MC68HC912D60C Colpitts Oscillator Specification 12.4.1.4 Input ESD Resistor Path Modification To satisfy the condition of oscillation, the oscillator circuit must not only provide the correct amount of gain but also the correct amount of phase shift. In the Colpitts configuration, the phase shift due to parasitics in the input path to the gate of the transconductance amplifier must be as low as possible.
Oscillator 12.4.2 MC68HC912D60C Oscillator Circuit Specifications 12.4.2.1 Negative Resistance Margin Negative Resistance Margin (NRM) is a figure of merit commonly used to qualify an oscillator circuit with a given resonator. NRM is an indicator of how much additional resistance in series with the resonator is tolerable while still maintaining oscillation.
Oscillator MC68HC912D60C Colpitts Oscillator Specification NRM measurement techniques can also generate misleading results when applied to Automatic Level Control (ALC) style oscillator circuits such as the D60x/Dx128x. Many NRM methods slowly increase series resistance until oscillation stops.
Oscillator 12.4.2.3 Optimizing Component Values The maximum ESR possible (given a worst-case Gain Margin of 2) is not the optimum operating point. In some cases, the frequency accuracy of the oscillator is important and in other cases satisfying the traditional NRM measurement technique is important.
Oscillator MC68HC912D60C Colpitts Oscillator Specification • VDDPLL Setting — The Voltage applied to the VDDPLL pin (Logic 1 means VDDPLL is tied to the same potential as VDD). • Resonator Frequency — The frequency of oscillation of the resonator. • Maximum ESR — The maximum effective series resistance (ESR) of the resonator. This figure must include any increases due to ageing, power dissipation, temperature, process variation or particle contamination. 12.4.
Oscillator variation or particle contamination). 3. Within this range, choose the EXTAL–XTAL capacitance closest to (CEXTAL–XTAL = 2*CL – 1pF). 4. If the ideal component is between two valid component values (the maximum ESR is sufficient for both component values), then choose the component with the highest maximum ESR or choose an available component between the two listed values. 5. Choose the size of the XTAL–VSS capacitance equal to the closest available size to (CXTAL–VSS = 0.82*CEXTAL–XTAL). 6.
Oscillator MC68HC912D60C Colpitts Oscillator Specification Table 12-1. MC68HC912D60C EXTAL–XTAL Capacitor Values vs. Maximum ESR, Shunt Capacitance, and VDDPLL setting Maximum ESR vs.
Oscillator Maximum ESR vs. EXTAL–XTAL capacitor value, 8MHz resonators Shunt Capacitance (pF) (VDDPLL=VDD) Shunt Capacitance (pF) (VDDPLL=0) 3 40 50 60 70 80 90 95 90 5 35 45 50 60 70 75 80 70 7 30 40 45 50 60 65 65 10 25 30 35 40 45 50 3 50 60 70 85 95 105 115 104 5 40 50 60 70 80 90 95 75 7 35 45 55 60 70 75 80 60 10 35 40 45 50 55 60 47pF 39pF 33pF 27pF 22pF 18pF 13pF 10pF 70 CEXTAL-XTAL (pF) Maximum ESR vs.
Oscillator MC68HC912D60C Colpitts Oscillator Specification 12.4.4 MC68HC912D60C DC Blocking Capacitor Guidelines Due to the placement of the resonator from EXTAL to VSS and the nature of the microcontroller’s inputs, there will be a DC bias voltage of approximately (VDD–2V) across the pins of the resonator. For some resonators, this can have long-term reliability issues. To remedy this situation, a DC-blocking capacitor can be placed in series with the crystal, as shown in Figure 12-3.
Oscillator BUF - CFLT 2 OTA + RFLT ALC + BIAS EN RFLT CFLT GM RESD EXTAL XTAL CX-EX 1nF DC-blocking capacitor Resonator CX-VSS CDC Figure 12-3. MC68HC912D60C Crystal with DC Blocking Capacitor Technical Data 192 MC68HC912D60A — Rev. 3.
Oscillator MC68HC912D60C Colpitts Oscillator Specification 12.4.5 MC68HC912D60C Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer.
Oscillator • NOTE: Minimize XTAL and EXTAL routing lengths to reduce EMC issues. EXTAL and XTAL routing resistances are less important than capacitances. Using minimum width traces is an acceptable trade-off to reduce capacitance. 12.5 MC68HC912D60P Pierce Oscillator Specification This section applies to the 3L02H mask set, which refers to the newest set of CGM improvements (to the MC68HC912D60A) with the Pierce oscillator configuration enabled. The name for these devices is MC68HC912D60P. 12.5.
Oscillator MC68HC912D60P Pierce Oscillator Specification BUF - CFLT 2 OTA + RFLT ALC + BIAS RFEEDBACK EN GM RESD EXTAL XTAL Resonator CEX-VSS CX-VSS Figure 12-4. MC68HC912D60P Pierce Oscillator Architecture There are the following primary differences between the previous Colpitts (‘A’) and new Pierce (‘P’) oscillator configurations: • Oscillator architecture was changed from Colpitts to Pierce. • Hysteresis was added to the clock input buffer to reduce sensitivity to noise.
Oscillator • The input ESD resistor from EXTAL to the gate of the oscillator amplifier was changed to provide a parallel path, reducing parasitic phase shift in the oscillator. 12.5.1.1 Oscillator Architecture Change from Colpitts to Pierce The primary difference from the ‘A’ to the ‘P’ versions of the MC68HC912D60 is the architecture, or configuration, of the oscillator. The previous version (‘A’) is connected in Colpitts configuration, where the resonator is connected between the EXTAL pin and VSS.
Oscillator MC68HC912D60P Pierce Oscillator Specification lower amplitude for the Pierce. The amplitude will still be sufficient for robust operation across process, temperature, and voltage variance. 12.5.1.2 Clock Buffer Hysteresis The input clock buffer uses an Operational Transconductance Amplifier (labeled ‘OTA’ in the figure above) followed by a digital buffer to amplify the input signal on the EXTAL pin into a full-swing clock for use by the clock generation section of the microcontroller.
Oscillator 12.5.1.3 Bias Current Process Optimization For proper oscillation, the gain margin of the oscillator must exceed one or the circuit will not oscillate. Process variance in the bias current (which controls the gain of the amplifier) can cause the gain margin to be much lower than typical. This can be as a result of either too much or too little current.
Oscillator MC68HC912D60P Pierce Oscillator Specification 12.5.2 MC68HC912D60P Oscillator Circuit Specifications 12.5.2.1 Negative Resistance Margin Negative Resistance Margin (NRM) is a figure of merit commonly used to qualify an oscillator circuit with a given resonator. NRM is an indicator of how much additional resistance in series with the resonator is tolerable while still maintaining oscillation.
Oscillator NRM measurement techniques can also generate misleading results when applied to Automatic Level Control (ALC) style oscillator circuits such as the D60x/Dx128x. Many NRM methods slowly increase series resistance until oscillation stops. ALC-style oscillators reduce the gain of the oscillator circuit after start-up to reduce current, so if the oscillator tends to have more gain than optimum it will be more tolerant of additional resistance after start-up than it will during the start-up process.
Oscillator MC68HC912D60P Pierce Oscillator Specification 12.5.2.3 Optimizing Component Values The maximum ESR possible (given a worst-case Gain Margin of 2) is not the optimum operating point. In some cases, the frequency accuracy of the oscillator is important and in other cases satisfying the traditional NRM measurement technique is important.
Oscillator • VDDPLL Setting — The Voltage applied to the VDDPLL pin (Logic 1 means VDDPLL is tied to the same potential as VDD). • Resonator Frequency — The frequency of oscillation of the resonator. • Maximum ESR — The maximum effective series resistance (ESR) of the resonator. This figure must include any increases due to ageing, power dissipation, temperature, process variation or particle contamination. 12.5.
Oscillator MC68HC912D60P Pierce Oscillator Specification variation or particle contamination). 3. Within this range, choose the EXTAL–VSS capacitance closest to (CEXTAL–VSS = 2*CL – 10pF). 4. If the ideal component is between two valid component values (the maximum ESR is sufficient for both component values), then choose the component with the highest maximum ESR or choose an available component between the two listed values. 5. Choose the size of the XTAL–VSS capacitance equal to EXTAL–VSS capacitance.
Oscillator Table 12-2. MC68HC912D60P EXTAL–VSS, XTAL–VSS Capacitor Values vs. Maximum ESR, Shunt Capacitance, and VDDPLL setting Maximum ESR vs.
Oscillator MC68HC912D60P Pierce Oscillator Specification Maximum ESR vs.
Oscillator 12.5.4 MC68HC912D60P Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer. In addition to published errata for the MC68HC912D60A, the following guidelines must be followed or failure in operation may occur.
Technical Data — MC68HC912D60A Section 13. Pulse Width Modulator 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.3 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13.4 PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.
Pulse Width Modulator possible to know where the count is with respect to the duty value and software can be used to make adjustments by turning the enable bit off and on. The four PWM channel outputs share general-purpose port P pins. Enabling PWM pins takes precedence over the general-purpose port. When PWM channels are not in use, the port pins may be used for discrete input/output.
Pulse Width Modulator Introduction CLOCK SOURCE (ECLK or Scaled ECLK) CENTR = 1 PWCNTx GATE (CLOCK EDGE SYNC) FROM PORT P DATA REGISTER RESET UP/DOWN (DUTY CYCLE) 8-BIT COMPARE = PWDTYx T Q (PERIOD) Q MUX MUX TO PIN DRIVER 8-BIT COMPARE = PWPERx PPOLx PWENx SYNC PPOL = 1 PPOL = 0 PWDTY (PWPER − PWDTY) × 2 PWPER × 2 PWDTY Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel MC68HC912D60A — Rev. 3.
Pulse Width Modulator PSBCK PSBCK IS BIT 0 OF PWCTL REGISTER. INTERNAL SIGNAL LIMBDM IS ‘1’ IF THE MCU IS IN BACKGROUND DEBUG MODE.
Pulse Width Modulator PWM Register Description CON23 — Concatenate PWM Channels 2 and 3 When concatenated, channel 2 becomes the high-order byte and channel 3 becomes the low-order byte. Channel 2 output pin is used as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clockselect control bits determines the clock source. Channel 3 output pin becomes a general purpose I/O. 0 = Channels 2 and 3 are separate 8-bit PWMs. 1 = Channels 2 and 3 are concatenated to create one 16-bit PWM channel.
Pulse Width Modulator PCKB2 – PCKB0 — Prescaler for Clock B Clock B is one of two clock sources which may be used for channels 2 and 3. These three bits determine the rate of clock B, as shown in Table 13-1. Table 13-1.
Pulse Width Modulator PWM Register Description PCLK0 — PWM Channel 0 Clock Select 0 = Clock A is the clock source for channel 0. 1 = Clock S0 is the clock source for channel 0. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may occur during the transition. The following four bits apply in left-aligned mode only: PPOL3 — PWM Channel 3 Polarity 0 = Channel 3 output is low at the beginning of the period; high when the duty count is reached.
Pulse Width Modulator Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 PWEN3 PWEN2 PWEN1 PWEN0 0 0 0 0 0 0 0 0 RESET: PWEN — PWM Enable $0042 Setting any of the PWENx bits causes the associated port P line to become an output regardless of the state of the associated data direction register (DDRP) bit. This does not change the state of the data direction bit. When PWENx returns to zero, the data direction bit controls I/O direction.
Pulse Width Modulator PWM Register Description PWEN0 — PWM Channel 0 Enable The pulse modulated signal will be available at port P, bit 0 when its clock source begins its next cycle. 0 = Channel 0 is disabled. 1 = Channel 0 is enabled. RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 Bit 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PWPRES — PWM Prescale Counter $0043 PWPRES is a free-running 7-bit counter. Read anytime. Write only in special mode (SMOD = 1).
Pulse Width Modulator Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 RESET: PWSCNT0 — PWM Scale Counter 0 Value $0045 PWSCNT0 is a down-counter that, upon reaching $00, loads the value of PWSCAL0. Read any time. Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 RESET: PWSCAL1 — PWM Scale Register 1 $0046 Read and write anytime.
Pulse Width Modulator PWM Register Description Bit 7 6 5 4 3 2 1 Bit 0 PWCNT0 Bit 7 6 5 4 3 2 1 Bit 0 $0048 PWCNT1 Bit 7 6 5 4 3 2 1 Bit 0 $0049 PWCNT2 Bit 7 6 5 4 3 2 1 Bit 0 $004A PWCNT3 Bit 7 6 5 4 3 2 1 Bit 0 $004B RESET: 0 0 0 0 0 0 0 0 PWCNTx — PWM Channel Counters Read and write anytime. A write will cause the PWM counter to reset to $00. In special mode, if DISCR = 1, a write does not reset the PWM counter.
Pulse Width Modulator Bit 7 6 5 4 3 2 1 Bit 0 PWPER0 Bit 7 6 5 4 3 2 1 Bit 0 $004C PWPER1 Bit 7 6 5 4 3 2 1 Bit 0 $004D PWPER2 Bit 7 6 5 4 3 2 1 Bit 0 $004E PWPER3 Bit 7 6 5 4 3 2 1 Bit 0 $004F RESET: 1 1 1 1 1 1 1 1 PWPERx — PWM Channel Period Registers Read and write anytime. The value in the period register determines the period of the associated PWM channel.
Pulse Width Modulator PWM Register Description The value in each duty register determines the duty of the associated PWM channel. When the duty value is equal to the counter value, the output changes state. If the register is written while the channel is enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. Reading this register returns the most recent value written.
Pulse Width Modulator RDPP — Reduced Drive of Port P 0 = All port P output pins have normal drive capability. 1 = All port P output pins have reduced drive capability. PUPP — Pull-Up Port P Enable 0 = All port P pins have an active pull-up device disabled. 1 = All port P pins have an active pull-up device enabled. PSBCK — PWM Stops while in Background Mode 0 = Allows PWM to continue while in background mode. 1 = Disable PWM input clock when the part is in background mode.
Pulse Width Modulator PWM Register Description Bit 7 6 5 4 3 2 1 Bit 0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PWM – – – – PWM3 PWM2 PWM1 PWM0 RESET: – – – – – – – – PORTP — Port P Data Register $0056 PORTP can be read anytime. PWM functions share port P pins 3 to 0 and take precedence over the general-purpose port when enabled. When configured as input, a read will return the pin level. When configured as output, a read will return the latched output data.
Pulse Width Modulator 13.4 PWM Boundary Cases The boundary conditions for the PWM channel duty registers and the PWM channel period registers cause these results: Table 13-2. PWM Left-Aligned Boundary Conditions PWDTYx $FF $FF ≥PWPERx ≥PWPERx – – PWPERx >$00 >$00 – – $00 $00 PPOLx 1 0 1 0 1 0 Output Low High High Low High Low Table 13-3.
Technical Data — MC68HC912D60A Section 14. Enhanced Capture Timer 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 14.3 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . 230 14.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 Timer and Modulus Counter Operation in Different Modes . . 261 14.
Enhanced Capture Timer This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds.
Enhanced Capture Timer Introduction ÷ 1, 2, ...
Enhanced Capture Timer ÷1, 2, ...
Enhanced Capture Timer Introduction Load holding register and reset pulse accumulator 0 PT0 Edge detector Delay counter EDG0 8-bit PAC0 (PACN0) PA0H holding register Interrupt 0 EDG1 PT1 Edge detector 8-bit PAC1 (PACN1) Delay counter Host CPU data bus PA1H holding register 0 EDG2 PT2 Edge detector 8-bit PAC2 (PACN2) Delay counter PA2H holding register Interrupt 0 EDG3 PT3 Edge detector Delay counter 8-bit PAC3 (PACN3) PA3H holding register Figure 14-3.
Enhanced Capture Timer To TCNT Counter CLK1 CLK0 Clock select (PAMOD) Edge detector PT7 PACLK PACLK / 256 Interrupt PACLK / 65536 Prescaled MCLK (TMSK2 bits PR2-PR0) 4:1 MUX 8-bit PAC3 (PACN3) 8-bit PAC2 (PACN2) MUX PACA M clock Intermodule Bus Divide by 64 Interrupt 8-bit PAC1 (PACN1) 8-bit PAC0 (PACN0) Delay counter PACB Edge detector PT0 Figure 14-4. 16-Bit Pulse Accumulators Block Diagram Technical Data 228 MC68HC912D60A — Rev. 3.
Enhanced Capture Timer Introduction Pulse accumulator A PAD OC7 (OM7=1 or OL7=1) or (OC7M7 = 1) Figure 14-5. Block Diagram for Port7 with Output compare / Pulse Accumulator A 16-bit Main Timer PTn Edge detector Delay counter Set CnF Interrupt TCn Input Capture Reg. TCnH I.C. Holding Reg. BUFEN • LATQ • TFMOD Figure 14-6. C3F-C0F Interrupt Flag Setting MC68HC912D60A — Rev. 3.
Enhanced Capture Timer 14.3 Enhanced Capture Timer Modes of Operation The Enhanced Capture Timer has 8 Input Capture, Output Compare (IC/OC) channels same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called Input Capture (IC) channels. Four IC channels are the same as on the standard timer with one capture register which memorizes the timer value captured by an action on the associated input pin.
Enhanced Capture Timer Enhanced Capture Timer Modes of Operation 14.3.1.1 Non-Buffered IC Channels The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless it is empty.
Enhanced Capture Timer If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see IC Channels).
Enhanced Capture Timer Timer Registers At the same time the pulse accumulator is cleared. 14.3.3 Modulus Down-Counter The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers. The action of latching can be programmed to be periodic or only once. 14.
Enhanced Capture Timer Bit 7 6 5 4 3 2 1 Bit 0 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 RESET: CFORC — Timer Compare Force Register $0081 Read anytime but will always return $00 (1 state is transient). Write anytime. FOC[7:0] — Force Output Compare Action for Channel 7-0 A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “n” to occur immediately.
Enhanced Capture Timer Timer Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 OC7D — Output Compare 7 Data Register $0083 Read or write anytime. The bits of OC7D correspond bit-for-bit with the bits of timer port (PORTT). When a successful OC7 compare occurs, for each bit that is set in OC7M, the corresponding data bit in OC7D is stored to the corresponding bit of the timer port.
Enhanced Capture Timer Bit 7 6 5 4 TEN TSWAI TSBCK TFFCA 0 0 0 0 RESET: 3 2 1 Bit 0 0 0 0 0 TSCR — Timer System Control Register $0086 Read or write anytime. TEN — Timer Enable 0 = Disables the main timer, including the counter. Can be used for reducing power consumption. 1 = Allows the timer to function normally. If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the E÷64 is generated by the timer prescaler.
Enhanced Capture Timer Timer Registers MCCNT register ($B6, $B7) clears the MCZF flag in the MCFLG register ($A7). This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
Enhanced Capture Timer Table 14-1. Compare Result Output Action OMn 0 0 1 1 OLn 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
Enhanced Capture Timer Timer Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 TMSK1 — Timer Interrupt Mask 1 $008C Read or write anytime. The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a hardware interrupt. Read or write anytime.
Enhanced Capture Timer RDPT — Timer Port Drive Reduction This bit reduces the effective output driver size which can reduce power supply current and generated noise depending upon pin loading. 0 = Normal output drive capability 1 = Enable output drive reduction function TCRE — Timer Counter Reset Enable This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter.
Enhanced Capture Timer Timer Registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 TFLG1 — Main Timer Interrupt Flag 1 $008E TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a one to the bit.
Enhanced Capture Timer TOF — Timer Overflow Flag Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.
Enhanced Capture Timer Timer Registers Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TC6 — Timer Input Capture/Output Compare Register 6 $009C–$009D Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TC7 — Timer Input Capture/Output Compare Register 7 $009E–$009F Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a
Enhanced Capture Timer PAEN — Pulse Accumulator A System Enable 0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPACR ($A8) are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 1 = Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator.
Enhanced Capture Timer Timer Registers If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since the E÷64 clock is generated by the timer prescaler.
Enhanced Capture Timer This bit is cleared automatically by a write to the PAFLG register with bit 1 set. PAIF — Pulse Accumulator Input edge Flag Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set.
Enhanced Capture Timer Timer Registers BIT 7 6 5 4 3 2 1 BIT 0 $00A4 BIt 7 6 5 4 3 2 1 Bit 0 PACN1 (hi) $00A5 Bit 7 6 5 4 3 2 1 Bit 0 PACN0 (lo) RESET: 0 0 0 0 0 0 0 0 PACN1, PACN0 — Pulse Accumulators Count Registers $00A4, $00A5 Read: any time Write: any time The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator.
Enhanced Capture Timer MODMC — Modulus Mode Enable 0 = The counter counts once from the value written to it and will stop at $0000. 1 = Modulus mode is enabled. When the counter reaches $0000, the counter is loaded with the latest value written to the modulus count register. NOTE: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to $FF.
Enhanced Capture Timer Timer Registers MCEN — Modulus Down-Counter Enable 0 = Modulus counter disabled. 1 = Modulus counter is enabled. When MCEN=0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. MCPR1, MCPR0 — Modulus Counter Prescaler select These two bits specify the division rate of the modulus counter prescaler.
Enhanced Capture Timer POLF3 – POLF0 — First Input Capture Polarity Status These are read only bits. Write to these bits has no effect. Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. Each POLFx corresponds to a timer PORTx input. 0 = The first input capture has been caused by a falling edge. 1 = The first input capture has been caused by a rising edge.
Enhanced Capture Timer Timer Registers RESET: BIT 7 6 5 4 3 2 1 BIT 0 0 0 0 0 0 0 DLY1 DLY0 0 0 0 0 0 0 0 0 DLYCT — Delay Counter Control Register $00A9 Read: any time Write: any time If enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected number of M clock (module clock) cycles, then it will generate a pulse on its output.
Enhanced Capture Timer An IC register is empty when it has been read or latched into the holding register. A holding register is empty when it has been read. NOVWx — No Input Capture Overwrite 0 = The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 = The related capture register or holding register cannot be written by an event unless they are empty (see IC Channels).
Enhanced Capture Timer Timer Registers the main timer contents. At the next event the TCn data is transferred to the TCnH register, The TCn is updated and the CnF interrupt flag is set. See Figure 14-6. In all other input capture cases the interrupt flag is set by a valid external event on PTn. 0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid input capture transition on the corresponding port pin occurs.
Enhanced Capture Timer 0 = Queue Mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. 1 = Latch Mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is written into the count register MCCNT (see Buffered IC Channels).
Enhanced Capture Timer Timer Registers BIT 7 6 5 4 3 2 1 BIT 0 PORT PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 TIMER I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0 RESET: 0 0 0 0 0 0 0 0 PORTT — Timer Port Data Register $00AE Read: any time (inputs return pin level; outputs return data register contents) Write: data stored in an internal latch (drives pins only if configured for output) Since the Output Compare 7 shares the pin with Pulse Accumulator input, the only way for Pulse
Enhanced Capture Timer BIT 7 6 5 4 3 2 1 BIT 0 DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0 0 0 0 0 0 0 0 0 RESET: DDRT — Data Direction Register for Timer Port $00AF Read or write any time. 0 = Configures the corresponding I/O pin for input only 1 = Configures the corresponding I/O pin for output. The timer forces the I/O state to be an output for each timer port line associated with an enabled output compare.
Enhanced Capture Timer Timer Registers 1 = Pulse Accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. PA1EN and PA0EN control bits in ICPACR ($A8) have no effect. PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled.
Enhanced Capture Timer BIT 7 6 5 4 3 2 1 BIT 0 $00B2 BIt 7 6 5 4 3 2 1 Bit 0 PA3H $00B3 Bit 7 6 5 4 3 2 1 Bit 0 PA2H $00B4 BIt 7 6 5 4 3 2 1 Bit 0 PA1H $00B5 Bit 7 6 5 4 3 2 1 Bit 0 PA0H RESET: 0 0 0 0 0 0 0 0 PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers $00B2–$00B5 Read: any time Write: has no effect.
Enhanced Capture Timer Timer Registers If a $0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS ($AB) register are set, the input capture and pulse accumulator registers will be latched. With a $0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag in MCFLG register. If modulus mode is enabled (MODMC=1), a write to this address will update the load register with the value written to it.
Enhanced Capture Timer Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TC0H — Timer Input Capture Holding Register 0 $00B8–$00B9 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TC1H — Timer Input Capture Holding Register 1 $00BA–$00BB Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TC2H — Timer Input Capture Holding Register 2 $00BC–$00BD Bi
Enhanced Capture Timer Timer and Modulus Counter Operation in Different Modes 14.5 Timer and Modulus Counter Operation in Different Modes STOP: Timer and modulus counter are off since clocks are stopped. BGDM: Timer and modulus counter keep on running, unless TSBCK (REG$86, bit5) is set to one. WAIT: Counters keep on running, unless TSWAI in TSCR ($86) is set to one. NORMAL: Timer and modulus counter keep on running, unless TEN in TSCR($86) respectively MCEN in MCCTL ($A6) are cleared.
Enhanced Capture Timer Technical Data 262 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 15. Multiple Serial Interface 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 15.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . 264 15.5 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . 276 15.6 Port S . . . . . . . . . . . . . . . . . . . .
Multiple Serial Interface 15.3 Block diagram SCI1 RxD0 PS0 TxD0 PS1 RxD1 TxD1 MISO/SISO SPI MOSI/MOMI PORT S I/O DRIVERS SCI0 DDRS/IOCTLR MSI PS2 PS3 PS4 PS5 SCK PS6 CS/SS PS7 Figure 15-1. Multiple Serial Interface Block Diagram 15.4 Serial Communication Interface (SCI) Two serial communication interfaces are available on the MC68HC912D60A.
Multiple Serial Interface Serial Communication Interface (SCI) MCLK BAUD RATE CLOCK SCI TRANSMITTER MSB DIVIDER Rx Baud Rate PARITY GENERATOR LSB 10-11 Bit SHIFT REG TxD BUFFER/SCxDRL PIN CONTROL / DDRS / PORT S SCxBD/SELECT Tx Baud Rate SCxCR1/SCI CTL 1 TxMTR CONTROL DATA BUS SCxCR2/SCI CTL 2 SCxSR1/INT STATUS TxD RxD INT REQUEST LOGIC TO INTERNAL LOGIC PARITY DETECT DATA RECOVERY SCI RECEIVER MSB LSB 10-11 BIT SHIFT REG TxD BUFFER/SCxDRL SCxCR1/SCI CTL 1 WAKE-UP LOGIC SCxSR1/INT STA
Multiple Serial Interface 15.4.1 Data Format The serial data format requires the following conditions: • An idle-line in the high state before transmission or reception of a message. • A start bit (logic zero), transmitted or received, that indicates the start of each character. • Data that is transmitted or received least significant bit (LSB) first. • A stop bit (logic one), used to indicate the end of a frame. (A frame consists of a start bit, a character of eight or nine data bits and a stop bit.
Multiple Serial Interface Serial Communication Interface (SCI) 15.4.3 SCI Register Descriptions Control and data registers for the SCI subsystem are described below. The memory address indicated for each register is the default address that is in use after reset. Both SCI have identical control registers mapped in two blocks of eight bytes.
Multiple Serial Interface BTST — Reserved for test function BSPL — Reserved for test function BRLD — Reserved for test function Bit 7 6 5 4 3 2 1 Bit 0 LOOPS WOMS RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 RESET: SC0CR1/SC1CR1 — SCI Control Register 1 $00C2/$00CA Read or write anytime. LOOPS — SCI LOOP Mode/Single Wire Mode Enable 0 = SCI transmit and receive sections operate normally.
Multiple Serial Interface Serial Communication Interface (SCI) RSRC — Receiver Source When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver. 0 = Receiver input is connected to the transmitter internally (not TXD pin) 1 = Receiver input is connected to the TXD pin Table 15-2.
Multiple Serial Interface In the long mode, the SCI circuitry does not begin counting ones in the search for the idle line condition until a stop bit is received. Therefore, the last byte’s stop bit and preceding “1” bits do not affect how quickly an idle line condition can be detected. PE — Parity Enable 0 = Parity is disabled. 1 = Parity is enabled. PT — Parity Type If parity is enabled, this bit determines even or odd parity for both the receiver and the transmitter. 0 = Even parity is selected.
Multiple Serial Interface Serial Communication Interface (SCI) RIE — Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled, RAF interrupt in WAIT mode disabled 1 = SCI interrupt will be requested whenever the RDRF or OR status flag is set, or when RAF is set while in WAIT mode with VDDPLL high. ILIE — Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt will be requested whenever the IDLE status flag is set.
Multiple Serial Interface Bit 7 6 5 4 3 2 1 Bit 0 TDRE TC RDRF IDLE OR NF FE PF 1 1 0 0 0 0 0 0 RESET: SC0SR1/SC1SR1 — SCI Status Register 1 $00C4/$00CC The bits in these registers are set by various conditions in the SCI hardware and are automatically cleared by special acknowledge sequences. The receive related flag bits in SCxSR1 (RDRF, IDLE, OR, NF, FE, and PF) are all cleared by a read of the SCxSR1 register followed by a read of the transmit/receive data register low byte.
Multiple Serial Interface Serial Communication Interface (SCI) RDRF — Receive Data Register Full Flag Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF is set if a received character is ready to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with RDRF set and then reading SCxDR. 0 = SCxDR empty 1 = SCxDR full IDLE — Idle Line Detected Flag Receiver idle line is detected (the receipt of a minimum of 10/11 consecutive ones).
Multiple Serial Interface PF — Parity Error Flag Indicates if received data’s parity matches parity bit. This feature is active only when parity is enabled. The type of parity tested for is determined by the PT (parity type) bit in SCxCR1. 0 = Parity correct 1 = Incorrect parity detected Bit 7 6 5 4 3 2 1 Bit 0 SCSWAI MIE(1) MDL1(1) MDL0(1) 0 0 0 RAF 0 0 0 0 0 0 0 0 RESET: SC0SR2 — SCI Status Register 2 $00C5/$00CD 1. See Freescale Interconnect Bus for descriptions of these bits.
Multiple Serial Interface Serial Communication Interface (SCI) RESET: Bit 7 6 5 4 3 2 1 Bit 0 R8 T8 0 0 0 0 0 0 — — — — — — — — SC0DRH/SC1DRH — SCI Data Register High RESET: $00C6/$00CE Bit 7 6 5 4 3 2 1 Bit 0 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 — — — — — — — — SC0DRL/SC1DRL — SCI Data Register Low $00C7/$00CF R8 — Receive Bit 8 Read anytime. Write has no meaning or affect.
Multiple Serial Interface 15.5 Serial Peripheral Interface (SPI) The serial peripheral interface allows the MC68HC912D60A to communicate synchronously with peripheral devices and other microprocessors. The SPI system in the MC68HC912D60A can operate as a master or as a slave. The SPI is also capable of interprocessor communications in a multiple master system.
Multiple Serial Interface Serial Peripheral Interface (SPI) MCU P CLOCK (SAME AS E RATE) DIVIDER ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256 8-BIT SHIFT REGISTER S M MISO PS4 M S MOSI PS5 READ DATA BUFFER SP0DR SPI DATA REGISTER LSBF SPR0 SP0SR SPI STATUS REGISTER M SS PS7 MSTR SPE SP0CR1 SPI CONTROL REGISTER 1 SPC0 RDS PUPS SSOE CPHA MSTR SWOM SPE SWOM SPIE MODF WCOL SPIF SPI INTERRUPT REQUEST SCK PS6 S CLOCK LOGIC SP0BR SPI BAUD RATE REGISTER SPI CONTROL PIN CONTROL LOGIC CLOCK CPOL
Multiple Serial Interface Begin Transfer End SCK (CPOL=0) SCK (CPOL=1) If next transfer begins here SAMPLE I (MOSI/MISO) CHANGE O (MOSI pin) CHANGE O (MISO pin) SEL SS (O) (Master only) SEL SS (I) MSB first (LSBF=0): LSB first (LSBF=1): tL MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB tT tL tI Minimum 1/2 SCK for tT, tl, tL Figure 15-4. SPI Clock Format 0 (CPHA = 0) Technical Data 278 MC68HC912D60A — Rev. 3.
Multiple Serial Interface Serial Peripheral Interface (SPI) Transfer Begin End SCK (CPOL=0) SCK (CPOL=1) If next transfer begins here SAMPLE I (MOSI/MISO) CHANGE O (MOSI pin) CHANGE O (MISO pin) SEL SS (O) (Master only) SEL SS (I) tL MSB first (LSBF=0): LSB first (LSBF=1): MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 tT tL tI LSB Minimum 1/2 SCK for tT, tl, tL MSB Figure 15-5. SPI Clock Format 1 (CPHA = 1) 15.5.
Multiple Serial Interface 15.5.4 Bidirectional Mode (MOMI or SISO) In bidirectional mode, the SPI uses only one serial data pin for external device interface. The MSTR bit decides which pin to be used. The MOSI pin becomes serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The direction of each serial I/O pin depends on the corresponding DDRS bit.
Multiple Serial Interface Serial Peripheral Interface (SPI) SPIE — SPI Interrupt Enable 0 = SPI interrupts are inhibited 1 = Hardware interrupt sequence is requested each time the SPIF or MODF status flag is set SPE — SPI System Enable 0 = SPI internal hardware is initialized and SPI system is in a lowpower disabled state. 1 = PS[4:7] are dedicated to the SPI function When MODF is set, SPE always reads zero. SP0CR1 must be written as part of a mode fault recovery sequence.
Multiple Serial Interface Normally data is transferred most significant bit first.This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register will always have MSB in bit 7. Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 SPSWAI SPC0 0 0 0 0 0 0 0 0 RESET: SP0CR2 — SPI Control Register 2 $00D1 Read or write anytime.
Multiple Serial Interface Serial Peripheral Interface (SPI) RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 SPR2 SPR1 SPR0 0 0 0 0 0 0 0 0 SP0BR — SPI Baud Rate Register $00D2 Read anytime. Write anytime. At reset, E Clock divided by 2 is selected. SPR[2:0] — SPI Clock (SCK) Rate Select Bits These bits are used to specify the SPI clock rate. Table 15-4.
Multiple Serial Interface WCOL — Write Collision Status Flag The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access (read or write) to the SP0DR register.
Multiple Serial Interface Port S some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. 15.6 Port S In all modes, port S bits PS[7:0] can be used for either general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as high-impedance inputs (DDRS is cleared).
Multiple Serial Interface DDS2, DDS0 — Data Direction for Port S Bit 2 and Bit 0 If the SCI receiver is configured for two-wire SCI operation, corresponding port S pins will be input regardless of the state of these bits. DDS3, DDS1 — Data Direction for Port S Bit 3 and Bit 1 If the SCI transmitter is configured for two-wire SCI operation, corresponding port S pins will be output regardless of the state of these bits.
Multiple Serial Interface Port S RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 RDPS2 RDPS1 RDPS0 0 PUPS2 PUPS1 PUPS0 0 0 0 0 0 0 0 0 PURDS — Pull-Up Register for Port S $00D9 RDPS2 — Reduce Drive of Port S[7:4] 0 = Port S[7:4] output drivers operate normally 1 = Port S[7:4] output pins have reduced drive capability for lower power and less noise RDPS1 — Reduce Drive of Port S[3:2] 0 = Port S[3:2] output drivers operate normally 1 = Port S[3:2] output pins have reduced drive capability for low
Multiple Serial Interface Technical Data 288 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 16. Freescale Interconnect Bus 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.3 Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.4 Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.5 Message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.6 Interfacing to MI Bus. . . . .
Freescale Interconnect Bus violates the rules of Manchester biphase encoding. Up to eight slave devices may be addressed by the MI Bus. Other features of MI Bus include message validation, error detection, and default value setting. On the MC68HC912D60A the MI Bus module shares the same pins on port S as the SCI0 module. Data is transmitted (or ‘pushed’) via the TxD0 pin, and received (‘pulled’) via the RxD0 pin. While data is being pushed, RxD0 will be disconnected from the receiver circuitry.
Freescale Interconnect Bus Biphase coding 16.3.1 The push field The push field consists of a start bit, a push synchronization bit, a push data field and a push address field. The start consists of three time slots having the dominant logical state ‘0’. The start marks the beginning of the message frame by violation of the rule of the Manchester code. The push synchronization bit consists of a biphase coded ‘0’. Biphase coding will be discussed later.
Freescale Interconnect Bus ‘0’ ‘1’ Biphase coded signal 0 1 2 3 4 5 a 6 7 0 1 b 2 3 4 5 a 6 7 t b Biphase detection a’ a b’ b a’ a b’ b Noise detection Figure 16-2. Biphase coding and error detection 16.
Freescale Interconnect Bus Message validation Transmit buffer T8 LOOPS 10/11-bit TX shift register H 8 7 RSRC M TxD0 0 L WAKE MCLK clock ILT PE MIE PT PT Transmitter control TE SBK TIE Rate generator Flag control TCIE ILIE MIE RE RE SC0BDL SC0CR2 RIE TE Receiver RWU control SBK WOMS SC0BDH SC0CR1 WOMS WOMS SCSWAI MIE SC0SR2 MDL1 10/11-bit RX shift register MDL0 8 7 RxD0 START R8 RAF Data recovery 0 STOP Receive buffer † † NF OR † TC RDRF TDRE SC0SR1 ID
Freescale Interconnect Bus 16.5.1 Controller detected errors There are three different MI Bus error types which are detected by the selected slave device and are not mutually exclusive. The MCU cannot determine which error occurred. Noise error — Slave devices take two samples in each time slot of the biphase encoded push field. An error occurs when the two samples for each time slot are not the same logical level. Biphase error — Slave devices receiving the push field detect the biphase code.
Freescale Interconnect Bus Interfacing to MI Bus VDD +12V 4.7kΩ 1.2kΩ 18V MI Bus VDD T1 TX 3.9kΩ VDD 10kΩ MCU 10kΩ 22kΩ RX VSS Figure 16-4. A typical MI Bus interface The transistor serves both to drive the MI Bus during the push field and to protect the MCU TX pin from voltage transients generated in the wiring. Without the transistor, EMI could damage the TX pin. Similarly, the input pin (RX) is protected from EMI by clamping it to the MCU supply rails with two diodes.
Freescale Interconnect Bus 16.7 MI Bus clock rate The MI Bus clock rate is set via the SCI baud registers. To use the MI Bus, the MCLK clock frequency that drives the SCI clock generator must be selected to match the minimum resolution of the MI Bus logic. This is expressed by the following formula: MCLK = 16 • n • (2 • Push_field_bit_rate) = 16 • n • 40kHz = n • 640kHz where ‘n’ is an integer and 20kHz is the minimum Push field bit rate for the MI Bus.
Freescale Interconnect Bus SCI0/MI Bus registers SC0BDH and SC0BDL are considered together as a 16-bit baud rate control register. Read any time. Write SBR[12:0] anytime. Low order byte must be written for change to take effect. Write SBR[15:13] only in special modes. The value in SBR[12:0] determines the clock rate of the MI Bus.
Freescale Interconnect Bus PT — MI Bus TxD0 polarity If parity is enabled, this bit determines even or odd parity for both the receiver and the transmitter. 0 = MI Bus transmit pin functions normally. 1 = MI Bus transmit pin will send inverted data. Bit 7 6 5 4 3 2 1 Bit 0 — — RIE — TE RE — SBK 0 0 0 0 0 0 0 0 RESET: SC0CR2 — MI Bus Control Register 2 $00C3 Read or write anytime. RIE — Receiver Interrupt Enable 0 = RDRF interrupt disabled.
Freescale Interconnect Bus SCI0/MI Bus registers RESET: Bit 7 6 5 4 3 2 1 Bit 0 — — RDRF — OR NF — — 1 1 0 0 0 0 0 0 SC0SR1 — MI Bus Status Register 1 $00C4 The bits in these registers are set by various conditions in the MI Bus hardware and are automatically cleared by special acknowledge sequences. The receive related flag bits in SC0SR1 (RDRF, OR and NF) are all cleared by a read of this register followed by a read of the transmit/receive data register low byte.
Freescale Interconnect Bus OR — Bit Error Flag 0 = No bit error has been detected. 1 = A bit error has been detected. This bit is set when a push field bit value on the MI Bus does not match the bit value that was sent. This is known as an MI Bus bit error. OR does not generate an interrupt request in MI Bus mode. NF — Noise Error Flag 0 = No noise detected. 1 = Noise detected. This bit is set when noise is detected on the receive line during an MI Bus pull field.
Freescale Interconnect Bus SCI0/MI Bus registers Table 16-1. MI Bus Delay Delay factor Delay time(1) MDL1 MDL0 0 0 1 0 1 1 1 0 1 2 3 4 1.5625 µs(2) 3.125 µs 4.6875 µs 6.25 µs 1. 20kHz bit rate requires 25µs (40kHz) time slots. 2.
Freescale Interconnect Bus WRITE: Writes access the eight bits of the write-only MI Bus transmit data register. MI Bus devices require a 5-bit data pattern followed by a 3-bit address pattern to be sent during the push field. The data pattern is mapped to the lowest five bits of the data register and the address to the highest three bits, as shown in the above table. Thus MI-data[4:0] is written to SC0DRL[4:0] and MI-address[2:0] is written to SC0DRL[7:5]. Technical Data 302 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 17. MSCAN Controller 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 17.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .310 17.6 Interrupts. . . . . . . . . . . . . . . .
MSCAN Controller real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. msCAN12 utilises an advanced buffer arrangement resulting in a predictable real-time behaviour and simplifies the application software. 17.3 External Pins The msCAN12 uses 2 external pins, 1 input (RxCAN) and 1 output (TxCAN). The TxCAN output pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state.
MSCAN Controller Message Storage CAN station 1 CAN station 2 ..... CAN station n CAN system msCAN12 Controller TxCAN RxCAN Transceiver CAN Figure 17-1. The CAN System 17.4 Message Storage msCAN12 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 17.4.1 Background Modern application layer software is built upon two fundamental assumptions: 1.
MSCAN Controller The above behaviour cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) in order to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds it requires that the CPU reacts with short latencies to the transmit interrupt.
MSCAN Controller Message Storage On reception, each message is checked to see if it passes the filter (for details see Identifier Acceptance Filter) and in parallel is written into RxBG. The msCAN12 copies the content of RxBG into RxFG(1), sets the RXF flag, and generates a receive interrupt to the CPU(2). The user’s receive handler has to read the received message from RxFG and then reset the RXF flag in order to acknowledge the interrupt and to release the foreground buffer.
MSCAN Controller msCAN12 CPU bus RxBG RxFG RXF Tx0 TXE PRIO Tx1 TXE PRIO Tx2 TXE PRIO Figure 17-2. User Model for Message Buffer Organization When the msCAN12 module is transmitting, the msCAN12 receives its own messages into the background receive buffer, RxBG, but does NOT overwrite RxFG, generate a receive interrupt or acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see msCAN12 Module Control Register 1 (CMCR1).
MSCAN Controller Message Storage An overrun condition occurs when both the foreground and the background receive message buffers are filled with correctly received messages with accepted identifiers and another message is correctly received from the bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled.
MSCAN Controller If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the msCAN12 uses the local priority setting of the three buffers for prioritisation. For this purpose every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being emitted from this node.
MSCAN Controller Identifier Acceptance Filter cause of the receiver interrupt. When more than one hit occurs (two or more filters match) the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced in order to reduce the CPU interrupt loading.
MSCAN Controller ID28 IDR0 ID10 IDR0 ID21 ID20 IDR1 ID3 ID2 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR IDR1 IDE AC7 CIDMRO AC0 AC7 CIDMR1 AC0 AC7 CIDMR2 AC0 AC7 CIDMR3 AC0 AC7 CIDARO AC0 AC7 CIDAR1 AC0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0 ID accepted (Filter 0 hit) Figure 17-3.
MSCAN Controller Identifier Acceptance Filter ID28 IDR0 ID21 ID20 ID10 IDR0 ID3 ID2 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR IDR1 IDE AC7 CIDMRO AC0 AC7 CIDARO AC0 ID accepted (Filter 0 hit) AC7 CIDMR1 AC0 AC7 CIDAR1 AC0 ID accepted (Filter 1 hit) AC7 CIDMR2 AC0 AC7 CIDAR2 AC0 ID accepted (Filter 2 hit) AC7 CIDMR3 AC0 AC7 CIDAR3 AC0 Figure 17-5. 8-bit Maskable Acceptance Filters MC68HC912D60A — Rev. 3.
MSCAN Controller 17.6 Interrupts The msCAN12 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for details see msCAN12 Receiver Flag Register (CRFLG) to msCAN12 Transmitter Control Register (CTCR)): • Transmit interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set.
MSCAN Controller Interrupts 17.6.1 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the msCAN12 receiver flag register (CRFLG) or the msCAN12 transmitter flag register (CTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in above registers must be reset within the interrupt handler in order to handshake the interrupt. The flags are reset through writing a 1 to the corresponding bit position.
MSCAN Controller 17.7 Protocol Violation Protection The msCAN12 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the msCAN12 cannot be modified while the msCAN12 is on-line.
MSCAN Controller Low Power Modes Mode and generate interrupts (registers can be accessed via background debug mode). Table 17-2. msCAN12 vs. CPU operating modes msCAN Mode CPU Mode WAIT STOP (1) POWER_DOWN CSWAI = X SLPAK = X SFTRES = X SLEEP SOFT_RESET Normal RUN CSWAI = 1 SLPAK = X SFTRES = X CSWAI = 0 SLPAK = 1 SFTRES = 0 CSWAI = 0 SLPAK = 0 SFTRES = 1 CSWAI = 0 SLPAK = 0 SFTRES = 0 CSWAI = X SLPAK = 1 SFTRES = 0 CSWAI = X SLPAK = 0 SFTRES = 1 CSWAI = X SLPAK = 0 SFTRES = 0 1.
MSCAN Controller operations whether the msCAN12 starts transmitting or goes into Sleep Mode directly. During Sleep Mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ) to go into Sleep Mode. When in Sleep Mode, the msCAN12 stops its internal clocks. However, clocks to allow register accesses still run. If the msCAN12 is in bus-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks.
MSCAN Controller Low Power Modes msCAN12 Running SLPRQ = 0 SLPAK = 0 MCU MCU or msCAN12 msCAN12 Sleeping SLEEP Request SLPRQ = 1 SLPAK = 1 SLPRQ = 1 SLPAK = 0 msCAN12 Figure 17-6. SLEEP Request / Acknowledge Cycle 17.8.2 msCAN12 SOFT_RESET Mode In SOFT_RESET mode, the msCAN12 is stopped. Registers can still be accessed. This mode is used to initialize the module configuration, bit timing, and the CAN message filter.
MSCAN Controller 17.8.3 msCAN12 POWER_DOWN Mode The msCAN12 is in POWER_DOWN mode when • the CPU is in STOP mode or • the CPU is in WAIT mode and the CSWAI bit is set (see msCAN12 Module Control Register 0 (CMCR0)). When entering the POWER_DOWN mode, the msCAN12 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. NOTE: The user is responsible for ensuring that the msCAN12 is not active when POWER_DOWN mode is entered.
MSCAN Controller Clock System receives the frames being sent by itself, a timer signal is also generated after a successful transmission. The previously described timer signal can be routed into the on-chip timer interface module (ECT). This signal is connected to the Timer n Channel m input(1) under the control of the timer link enable (TLNKEN) bit in the CMCR0.
MSCAN Controller NOTE: If the system clock is generated from a PLL, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster CAN bus rates. For microcontrollers without the CGM module, CGMCANCLK is driven from the crystal oscillator (EXTALi). A programmable prescaler is used to generate out of msCANCLK the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the msCAN12.
MSCAN Controller Clock System NRZ Signal SYNC _SEG Time segment 1 (PROP_SEG + PHASE_SEG1) Time Seg. 2 (PHASE_SEG2) 1 4 ... 16 2 ... 8 8... 25 Time Quanta = 1 Bit Time Transmit point Sample point (single or triple sampling) Figure 17-8. Segments within the Bit Time Table 17-3. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 TSEG1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 ..
MSCAN Controller 17.11 Memory Map The msCAN12 occupies 128 bytes in the CPU12 memory space. The background receive buffer can only be read in test mode. Figure 17-9.
MSCAN Controller Programmer’s Model of Message Storage 17.12 Programmer’s Model of Message Storage The following section details the organisation of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
MSCAN Controller NOTE: ADDR(1) REGISTER $01x0 IDR0 $01x1 IDR1 $01x2 IDR2 $01x3 IDR3 $01x4 DSR0 $01x5 DSR1 $01x6 DSR2 $01x7 DSR3 $01x8 DSR4 $01x9 DSR5 $01xA DSR6 $01xB DSR7 $01xC DLR The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime.
MSCAN Controller Programmer’s Model of Message Storage ADDR(1) REGISTER $01x0 IDR0 $01x1 IDR1 $01x2 IDR2 $01x3 IDR3 R/W R W R W BIT 7 6 5 4 3 2 1 BIT 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE(0) R W R W Figure 17-12 1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively. 17.12.2 Identifier Registers (IDRn) The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29 bits (ID28–ID0) for the extended format.
MSCAN Controller RTR — Remote transmission request This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer this flag defines the setting of the RTR bit to be sent. 0 = Data frame 1 = Remote frame 17.12.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame.
MSCAN Controller Programmer’s Model of Message Storage 17.12.4 Data Segment Registers (DSRn) The eight data segment registers contain the data to be transmitted or being received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR. 17.12.
MSCAN Controller 17.13 Programmer’s Model of Control Registers 17.13.1 Overview The programmer’s model has been laid out for maximum simplicity and efficiency. 17.13.2 msCAN12 Module Control Register 0 (CMCR0) CMCR0 R Bit 7 6 0 0 5 4 SYNCH CSWAI $0100 3 2 1 Bit 0 SLPRQ SFTRES 0 1 SLPAK TLNKEN W RESET 0 0 1 0 0 0 CSWAI — CAN Stops in Wait Mode 0 = The module is not affected during WAIT mode. 1 = The module ceases to be clocked during WAIT mode.
MSCAN Controller Programmer’s Model of Control Registers SLPAK — SLEEP Mode Acknowledge This flag indicates whether the msCAN12 is in module internal SLEEP Mode. It shall be used as a handshake for the SLEEP Mode request (see msCAN12 SLEEP Mode). 0 = Wake-up – The msCAN12 is not in SLEEP Mode. 1 = SLEEP – The msCAN12 is in SLEEP Mode. SLPRQ — SLEEP request This flag allows to request the msCAN12 to go into an internal powersaving mode (see msCAN12 SLEEP Mode).
MSCAN Controller 17.13.3 msCAN12 Module Control Register 1 (CMCR1). CMCR1 R $0101 W RESET Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 1 Bit 0 LOOPB WUPM CLKSRC 0 0 0 LOOPB — Loop Back Self Test Mode When this bit is set the msCAN12 performs an internal loop back which can be used for self test operation: the bit stream output of the transmitter is fed back to the receiver internally. The RxCAN input pin is ignored and the TxCAN output goes to the recessive state (1).
MSCAN Controller Programmer’s Model of Control Registers 17.13.4 msCAN12 Bus Timing Register 0 (CBTR0) CBTR0 R $0102 W RESET Bit 7 6 5 4 3 2 1 Bit 0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 0 0 0 0 0 0 0 SJW1, SJW0 — Synchronization Jump Width The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see Table 17-5). Table 17-5.
MSCAN Controller 17.13.5 msCAN12 Bus Timing Register 1 (CBTR1). CBTR1 R $0103 W RESET Bit 7 6 5 4 3 2 1 Bit 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 0 SAMP — Sampling This bit determines the number of samples of the serial bus to be taken per bit time. If set three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule.
MSCAN Controller Programmer’s Model of Control Registers Table 17-8. Time segment values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle 0 0 0 1 2 Tq clock cycles 0 0 1 0 3 Tq clock cycles 0 0 1 1 4 Tq clock cycles . . . . . . . . . . 1 1 1 1 16 Tq clock cycles TSEG22 TSEG21 TSEG20 0 0 0 0 0 1 . . . . . . 1 1 1 Time segment 2 1 Tq clock cycle 2 Tq clock cycles . .
MSCAN Controller RWRNIF — Receiver Warning Interrupt Flag This flag is set when the msCAN12 goes into warning status due to the Receive Error counter (REC) exceeding 96 and neither one of the Error interrupt flags or the Bus-Off interrupt flag is set(1). If not masked, an Error interrupt is pending while this flag is set. 0 = No receiver warning status has been reached. 1 = msCAN12 went into receiver warning status.
MSCAN Controller Programmer’s Model of Control Registers BOFFIF — BUSOFF Interrupt Flag This flag is set when the msCAN12 goes into BUSOFF status, due to the Transmit Error counter exceeding 255. It cannot be cleared before the msCAN12 has monitored 128 times 11 consecutive recessive bits on the bus. If not masked, an Error interrupt is pending while this flag is set. 0 = No BUSOFF status has been reached. 1 = msCAN12 went into BUSOFF status.
MSCAN Controller 17.13.7 msCAN12 Receiver Interrupt Enable Register (CRIER) CRIER R $0105 W RESET Bit 7 6 5 4 3 2 1 Bit 0 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE 0 0 0 0 0 0 0 0 WUPIE — Wake-up Interrupt Enable 0 = No interrupt is generated from this event. 1 = A wake-up event results in a wake-up interrupt. RWRNIE — Receiver Warning Interrupt Enable 0 = No interrupt is generated from this event. 1 = A receiver warning status event results in an error interrupt.
MSCAN Controller Programmer’s Model of Control Registers RXFIE — Receiver Full Interrupt Enable 0 = No interrupt is generated from this event. 1 = A receive buffer full (successful message reception) event results in a receive interrupt. NOTE: The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set. 17.13.8 msCAN12 Transmitter Flag Register (CTFLG) The Abort Acknowledge flags are read only. The Transmitter Buffer Empty flags are read and clear only.
MSCAN Controller transmission request was successfully aborted due to a pending abort request (msCAN12 Transmitter Control Register (CTCR)). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx flag (see above). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see msCAN12 Transmitter Control Register (CTCR)). 0 = The associated message buffer is full (loaded with a message due for transmission).
MSCAN Controller Programmer’s Model of Control Registers TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable 0 = No interrupt will be generated from this event. 1 = A transmitter empty (transmit buffer available for transmission) event will result in a transmitter empty interrupt. NOTE: The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set. 17.13.
MSCAN Controller IDHIT2 – IDHIT0 — Identifier Acceptance Hit Indicator The msCAN12 sets these flags to indicate an identifier acceptance hit (see Identifier Acceptance Filter). Table 17-8 summarizes the different settings. Table 17-10.
MSCAN Controller Programmer’s Model of Control Registers 17.13.12 msCAN12 Transmit Error Counter (CTXERR) CTXERR R $010F W RESET Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 This register reflects the status of the msCAN12 transmit error counter. The register is read only. NOTE: Both error counters must only be read when in SLEEP or SOFT_RESET mode. 17.13.
MSCAN Controller CIDAR0 R $0110 W CIDAR1 R $0111 W CIDAR2 R $0112 W CIDAR3 R $0113 W RESET CIDAR4 R $0118 W CIDAR5 R $0119 W CIDAR6 R $011A W CIDAR7 R $011B W RESET Bit 7 6 5 4 3 2 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 – – – – – – – – Bit 7 6 5 4 3 2 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 A
MSCAN Controller Programmer’s Model of Control Registers 17.13.14 msCAN12 Identifier Mask Registers (CIDMR0–7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode it is required to program the last three bits (AM2–AM0) in the mask registers CIDMR1 and CIDMR5 to ‘don’t care’.
MSCAN Controller AM7 – AM0 — Acceptance Mask Bits If a particular bit in this register is cleared this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit, before a match is detected. The messageis accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted.
MSCAN Controller 17.13.16 msCAN12 Port CAN Data Register (PORTCAN) Bit 7 6 5 4 3 2 PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 0 0 0 0 0 0 PORTCAN R $013E 1 Bit 0 TxCAN RxCAN 0 0 W RESET PCAN7 – PCAN2 — Port CAN Data Bits (not available in 80QFP) Writing to PCANx stores the bit value in an internal bit memory. This value is driven to the respective pin only if DDCANx = 1.
MSCAN Controller Technical Data 348 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 18. Analog-to-Digital Converter 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 18.5 ATD Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 18.6 ATD Operation In Different MCU Modes . .
Analog-to-Digital Converter 18.2.
Analog-to-Digital Converter Modes of Operation 18.3 Modes of Operation Analog to digital conversions are performed in a variety of different programmable sequences referred to as conversion modes.
Analog-to-Digital Converter • WAIT is executed (if the ASWAI bit is activated) • STOP is executed. The MCU can discover when result data is available in the result registers with an interrupt on sequence complete or by polling the conversion complete flags NOTE: • The SCF bit is set after the completion of each sequence. • The CCF bit associated with each result register is set when that register is loaded with result data.
Analog-to-Digital Converter Functional Description 18.4.3 Sample and Hold Stage A Sample and Hold (S/H) stage accepts the analog signal from the input multiplexer and stores it as a capacitor charge on a storage node in the module. The sample process uses a three stage approach: 1. The input signal is sampled onto a sample capacitor (for 2 module clocks). 2. The sample amplifier quickly charges the storage node with a copy of the sample capacitor potential (for 4 module clocks). 3.
Analog-to-Digital Converter programmable constant in order to generate the ATD module’s internal clock. One additional benefit of the prescaled clock feature is that it allows the user further control over the sample period (note that changing the module clock also affects conversion time). The prescaler is based on a 5 bit modulus counter and divides the PCLK by an integer value between 1 and 32. The final clock frequency is obtained with a further division by 2.
Analog-to-Digital Converter ATD Operation In Different MCU Modes can be performed. Note that powering up the module does not reset the module since the register file is not initialized. In power down mode, the control and result registers are still accessible. 18.5.2 IDLE Mode IDLE mode for the ATD module is defined as the state where the ATD module is powered up and ready to perform an A/D conversion, but not actually performing a conversion at the present time.
Analog-to-Digital Converter 18.6.2 WAIT Mode If the ASWAI control bit in ATDCTL2 is set, then the ATD responds to WAIT mode. If the ASWAI control bit is clear, then the ATD ignores the WAIT signal. The ATD response to the wait mode is to power down the module. In this mode, the MCU does not have access to the control, status or result registers. 18.6.3 Background Debug (ATD FREEZE) Mode When debugging an application, it is useful to have the ATD pause when a breakpoint is encountered.
Analog-to-Digital Converter General Purpose Digital Input Port Operation The ATD module reset function places the module back into an initialized state. If the module is performing a conversion sequence, both the current conversion and the sequence are terminated. The conversion complete flags are cleared and any pending interrupts are cancelled.
Analog-to-Digital Converter 18.8 Application Considerations Note that the A/D converter’s accuracy is limited by the accuracy of the reference potentials. Noise on the reference potentials will result in noise on the digital output data stream: the reference potential lines do not reject reference noise. The reference potential pins must have a low AC impedance path back to the source. A large bypass capacitor (100nF or larger) will suffice in most cases.
Analog-to-Digital Converter ATD Registers 18.9.1 ATD Control Registers 0 &1 (ATDCTL0, ATDCTL1) ATD0CTL0/ATD1CTL0 — Reserved RESET: $0060/$01E0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Writes to this register will abort current conversion sequence. Read or write any time. ATD0CTL1/ATD1CTL1 — Reserved RESET: $0061/$01E1 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 WRITE: Write to this register has no meaning. READ: Special Mode only. 18.9.
Analog-to-Digital Converter This bit provides program on/off control over the ATD module allowing reduced MCU power consumption when the ATD is not being used. When reset to zero, the ADPU bit aborts any conversion sequence in progress. Because the analog electronics is turned off when powered down, the ATD requires a recovery time period when ADPU bit is enabled.
Analog-to-Digital Converter ATD Registers exited, the ATD module powers up and continues operation. The module is not reset; the register file is not reinitialized; the conversion sequence is not restarted. When the module comes out of wait, it is recommended that a stabilization delay ( tSR) is allowed before new conversions are started.
Analog-to-Digital Converter Input Signal Vrl = 0 Volts Vrh = 5.12 Volts 5.120 Volts 5.100 5.080 8-Bit Codes 10-Bit Codes FF FF FE FFC0 FF00 FE00 2.580 2.560 2.540 81 80 7F 8100 8000 7F00 0.020 0.000 01 00 0100 0000 Table 18-2. Left Justified ATD Output Codes ASCIE — ATD Sequence Complete Interrupt Enable 0 = Disables ATD interrupt 1 = Enables ATD interrupt on Sequence Complete The sequence complete interrupt function signals the MCU when a conversion sequence is complete.
Analog-to-Digital Converter ATD Registers ATD0CTL3/ATD1CTL3 — ATD Control Register 3 RESET: Bit 7 0 0 6 0 0 5 0 0 $0063/$01E3 4 0 0 3 S1C 0 2 FIFO 0 1 FRZ1 0 Bit 0 FRZ0 0 READ: any time WRITE: any time S1C — Conversion Sequence Length (Least Significant Bit) This control bit works with control bit S8C in ATDCTL5 in determining how many conversion are performed per sequence. When the S1C bit is set, a sequence length of 1 is defined.
Analog-to-Digital Converter Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. FRZ1, FRZ0 — Background Debug Freeze Enable Background debug freeze function allows the ATD module to pause when a breakpoint is encountered. Table 18-3 shows how FRZ1 and FRZ0 determine the ATD’s response to a breakpoint.
Analog-to-Digital Converter ATD Registers RES10 — A/D Resolution Select 0 = 8-bit resolution selected 1 = 10-bit resolution selected This bit determines the resolution of the A/D converter: 8-bits or 10bits. The A/D converter has the accuracy of a 10-bit converter. However, if low resolution is adequate, the conversion can be speeded up by selecting 8-bit resolution.
Analog-to-Digital Converter Table 18-5. Clock Prescaler Values Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01xxx 1xxxx Total Divisor Max PCLK(1) Min PCLK(2) ÷2 ÷4 ÷6 ÷8 ÷10 ÷12 ÷14 ÷16 4 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz Do Not Use 1. Maximum conversion frequency is 2 MHz. Maximum PCLK divisor value will become maximum conversion rate that can be used on this ATD module. 2. Minimum conversion frequency is 500 kHz.
Analog-to-Digital Converter ATD Registers S8C S1C 0 0 1 0 1 X Number of Conversions per Sequence 4 1 8 Table 18-6. Conversion Sequence Length Coding The result register assignments made to a conversion sequence follow a few simple rules. Normally, the first result is placed in the first register; the second result is placed in the second register, and so on. Table 187 presents the result register assignments for the various conversion lengths that are normally made.
Analog-to-Digital Converter mode is required, the existing continuous sequence must be interrupted, the control registers modified, and a new conversion sequence initiated. MULT — Multi-Channel Sample Mode 0 = Sample only the specified channel 1 = Sample across many channels When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CC/CB/CA located in ATDCTL5).
Analog-to-Digital Converter ATD Registers Table 18-8 lists the special channels. The last column in the table denote the expected digital code that should be generated by the special conversion for 8-bit resolution. CC, CB, CA — Analog Input Channel Select Code These bits select the analog input channel(s). Table 18-9 lists the coding used to select the various analog input channels. In the case of single channel scans (MULT=0), this selection code specifies the channel for conversion.
Analog-to-Digital Converter Table 18-10. Multichannel Mode Result Register Assignment (MULT=1) 4 channel conversion, External channels (S8C = 0, SC = 0) CC 0 0 0 0 CB 0 0 1 1 CA 0 1 0 1 ADR0 AN0 AN1 AN2 AN3 ADR1 AN1 AN2 AN3 AN4 ADR2 AN2 AN3 AN4 AN5 ADR3 AN3 AN4 AN5 AN6 1 0 0 AN4 AN5 AN6 AN7 1 0 1 AN5 AN6 AN7 AN0 1 1 0 AN6 AN7 AN0 AN1 1 1 1 AN7 AN0 AN1 AN2 1 0 0 VRH VRL MID 1 0 1 VRL MID 1 1 0 MID 1 1 1 S1C bit must be clear.
Analog-to-Digital Converter ATD Registers Table 18-10.
Analog-to-Digital Converter 18.9.5 ATDSTAT A/D Status Register The ATD Status registers contain the conversion complete flags and the conversion sequence counter. The status registers are read-only.
Analog-to-Digital Converter ATD Registers the result is available in result register ADR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ADR1, and so forth. The conversion complete flags are cleared depending on the setting of the fast flag clear bit (AFFC in ATDCTL2). When AFFC=0, the status register containing the conversion complete flag must be read as a precondition before the flag can be cleared.
Analog-to-Digital Converter 18.9.6 ATDTEST Module Test Register (ATDTEST) The test registers implement various special (test) modes used to test the ATD module. The reset bit in ATDTEST1 is always read/write. The SAR (successive approximation register) can always be read but only written in special (test) mode. The functions implemented by the test registers are reserved for factory test.
Analog-to-Digital Converter ATD Registers Resetting to idle mode defines the only exception of the reset control bit condition to the system reset condition. The reset control bit does not initialize the ADPU bit to its reset condition and therefore does not power down the module. This except allows the module to remain active for other test operations. 18.9.7 PORTAD Port Data Register The input data port associated with the ATD module is input-only. The port pins are shared with the analog A/D inputs.
Analog-to-Digital Converter 18.9.
Technical Data — MC68HC912D60A Section 19. Development Support 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 19.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 19.4 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 19.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 19.6 Instruction Tagging . . . . . . . . . . .
Development Support Table 19-1. IPIPE Decoding Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock(1) IPIPE[1:0] Mnemonic Meaning 0:0 — No Movement 0:1 LAT Latch Data From Bus 1:0 ALD Advance Queue and Load From Bus 1:1 ALL Advance Queue and Load From Latch Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock(2) IPIPE[1:0] Mnemonic Meaning 0:0 — No Start 0:1 INT Start Interrupt Sequence 1:0 SEV Start Even Instruction 1:1 SOD Start Odd Instruction 1.
Development Support Background Debug Mode 19.4 Background Debug Mode Background debug mode (BDM) is used for system development, incircuit testing, field testing, and programming. BDM is implemented in on-chip hardware and provides a full set of debug options. Because BDM control logic does not reside in the CPU, BDM hardware commands can be executed while the CPU is operating normally.
Development Support In special single-chip mode, background operation is enabled and active immediately out of reset. This active case replaces the M68HC11 boot function, and allows programming a system with blank memory. While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The BDM control logic uses these registers which can be read anytime by BDM logic, not user programs. Refer to BDM Registers for detailed descriptions.
Development Support Background Debug Mode BKGD pin during host-to-target transmissions to speed up rising edges. Since the target does not drive the BKGD pin during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions. BDMCLK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 PERCEIVED START OF BIT TIME TARGET SENSES BIT EARLIEST START OF NEXT BIT 10 CYCLES SYNCHRONIZATION UNCERTAINTY Figure 19-1.
Development Support Figure 19-2 shows the host receiving a logic one from the target MC68HC912D60A MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target B cycles).
Development Support Background Debug Mode 19.4.3 BDM Commands The BDM command set consists of two types: hardware and firmware. Hardware commands allow target system memory to be read or written. Target system memory includes all memory that is accessible by the CPU12 including EEPROM, on-chip I/O and control registers, and external memory that is connected to the target HC12 MCU. Hardware commands are implemented in hardware logic and do not require the HC12 MCU to be in BDM mode for execution.
Development Support Table 19-2.
Development Support Background Debug Mode Table 19-3.
Development Support The external host should delay about 32 target BDMCLK cycles after the data portion of firmware write commands to allow BDM firmware to complete the requested write operation before a new serial command disturbs the BDM SHIFTER register. The external host should delay about 64 target BDMCLK cycles after a TRACE1 or GO command before starting any new serial command.
Development Support Background Debug Mode program other bits of the SHADOW byte (location $0FC0); otherwise some regular EEPROM array locations will not be visible. At the next reset, the SHADOW byte is loaded into the EEMCR register. NOBDML bit in EEMCR will be cleared and BDM will not be operational. 4. Protect the SHADOW byte by setting SHPROT bit in EEPROT register. 19.4.4.2 Disabling BDM lockout Disabling the BDM lockout is only possible in special modes (SMODN=0) except in special single chip mode.
Development Support • The ADDRESS register is temporary storage for BDM commands. • The CCRSAV register preserves the content of the CPU12 CCR while BDM is active. The only registers of interest to users are the STATUS register and the CCRSAV register. The other BDM registers are only used by the BDM firmware to execute commands.
Development Support Background Debug Mode BDMACT — Background Mode Active Status BDMACT becomes set as active BDM mode is entered so that the BDM firmware ROM is enabled and put into the map. BDMACT is cleared by a carefully timed store instruction in the BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. This bit has 4 clock cycles write delay. 0 = BDM is not active. BDM ROM and registers are not in map.
Development Support CLKSW — BDMCLK Clock Switch 0 = BDM system operates with BCLK. 1 = BDM system operates with ECLK. The WRITE_BD_BYTE@FF01 command that changes CLKSW including 150 cycles after the data portion of the command should be timed at the old speed. Beginning with the start of the next BDM command, the new clock can be used for timing BDM communications. If ECLK rate is slower than BDMCLK rate, CLKSW is ignored and BDM system is forced to operate with ECLK. 19.4.5.
Development Support Background Debug Mode DATA — Data Flag - Shows that data accompanies the command.
Development Support R/W — Read/Write Flag 0 = Write 1 = Read TTAGO — Trace, Tag, Go Field Table 19-5. TTAGO Decoding Table 19-6TTAGO Value Table 19-7Instruction 00 — 01 GO 10 TRACE1 11 TAGGO REGN — Register/Next Field Indicates which register is being affected by a command. In the case of a READ_NEXT or WRITE_NEXT command, index register X is pre-incriminated by 2 and the word pointed to by X is then read or written. Table 19-8.
Development Support Background Debug Mode 19.4.5.3 SHIFTER This 16-bit shift register contains data being received or transmitted via the serial interface. It is also used by the BDM firmware for temporary storage.
Development Support 19.4.5.4 ADDRESS This 16-bit address register is temporary storage for BDM hardware and firmware commands.
Development Support Breakpoints 19.4.5.5 CCRSAV The CCRSAV register is used to save the CCR of the users program when entering BDM. It is also used for temporary storage in the BDM firmware. Read and write: all modes RESET: NOTE 1 (1) BIT 7 6 5 4 3 2 1 BIT 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 X X X X X X X X CCRSAV— BDM CCR Holding Register $FF06 1. Initialized to equal the CPU12 CCR register by the firmware. 19.
Development Support 19.5.1 Breakpoint Modes Three modes of operation determine the type of breakpoint in effect. • Dual address-only breakpoints, each of which will cause a software interrupt (SWI) • Single full-feature breakpoint which will cause the part to enter background debug mode (BDM) • Dual address-only breakpoints, each of which will cause the part to enter BDM Breakpoints will not occur when BDM is active. 19.5.1.
Development Support Breakpoints • There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. 19.5.1.3 BDM Dual Address Mode Dual address-only breakpoints, each of which cause the part to enter background debug mode. In the dual mode each address breakpoint is affected, consistent across modes, by the BKPM bit, the BKALE bit, and the BKxRW and BKxRWE bits. In dual address mode the BKDBE becomes an enable for the second address breakpoint.
Development Support To trace program flow, setting the BKPM bit causes address comparison of program data only. Control bits are also available that allow checking read/write matches. Bit 7 6 5 4 3 2 1 Bit 0 BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0 0 0 0 0 0 0 0 0 RESET: BRKCT0 — Breakpoint Control Register 0 $0020 Read and write anytime. This register is used to control the breakpoint logic. BKEN1, BKEN0 — Breakpoint Mode Enable Table 19-9.
Development Support Breakpoints BK0ALE — Breakpoint 0 Range Control Valid in all modes. 0 = BRKAL will not be used to compare to the address bus. 1 = BRKAL will be used to compare to the address bus. Table 19-10.
Development Support BKMBL — Breakpoint Mask Low Disables the matching of the low byte of data when in full breakpoint mode. Used in conjunction with the BKDBE bit (which should be set) 0 = Low byte of data bus (bits 7:0) are compared to BRKDL 1 = Low byte is not used in comparisons. BK1RWE — R/W Compare Enable Enables the comparison of the R/W signal to further specify what causes a match. This bit is NOT useful in program breakpoints or in full breakpoint mode.
Development Support Breakpoints Table 19-11.
Development Support Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 RESET: BRKDH — Breakpoint Data Register, High Byte $0024 These bits are compared to the most significant byte of the data bus or the most significant byte of the address bus in dual address modes. BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the breakpoint comparison.
Development Support TAGHI signal shares a pin with the BKGD signal. Tagging information is latched on the falling edge of ECLK. Table 19-12 shows the functions of the two tagging pins. The pins operate independently - the state of one pin does not affect the function of the other. The presence of logic level zero on either pin at the fall of ECLK performs the indicated function. Tagging is allowed in all modes.
Development Support Technical Data 404 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 20. Electrical Specifications 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 20.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 20.2 Introduction This section contains the most accurate electrical information for the MC68HC912D60A microcontroller. This is a 16-bit device available in two package options, 80-pin QFP and 112-pin TQFP.
Electrical Specifications 20.3 Tables of Data Table 20-1. Maximum Ratings(1) Rating Supply voltage Input voltage Operating temperature range MC912D60xCPV8 MC912D60xVPV8 MC912D60xMPV8 (single chip mode only) Operating temperature range MC912D60xCFU8 MC912D60xVFU8 MC912D60xMFU8 (single chip mode only) Storage temperature range Current drain per pin(2) Excluding VDD and VSS VDD differential voltage Symbol Value Unit VDD, VDDA, VDDX, VDDPLL −0.3 to +6.5 V VIN −0.3 to +6.
Electrical Specifications Tables of Data Table 20-2.
Electrical Specifications Table 20-3. DC Electrical Characteristics VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic Symbol Min Max Unit Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V Input low voltage, all inputs VIL VSS−0.3 0.2 × VDD V Output high voltage, all I/O and output pins except XTAL Normal drive strength IOH = −10.0 µA IOH = −0.8 mA Reduced drive strength IOH = −4.0 µA IOH = −0.3 mA VOH VDD − 0.2 VDD − 0.8 — — V V VDD − 0.
Electrical Specifications Tables of Data Table 20-4. Supply Current VDD = 5.
Electrical Specifications Table 20-6. Analog Converter Characteristics (Operating) VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted Characteristic Symbol 8-bit resolution(1) Min Typical 1 count 8-bit absolute error,(2)2, 4, 8, and 16 ATD sample clocks 10-bit resolution(1) Unit 20 mV −1 AE +1 1 count 10-bit absolute error(2) 2, 4, 8, and 16 ATD sample clocks Max count 5 AE mV –2.5 2.5 count 1. At VRH – VRL = 5.
Electrical Specifications Tables of Data Table 20-8. ATD Maximum Ratings Characteristic Symbol Value Units ATD reference voltage VRH ≤ VDDA VRL ≥ VSSA VRH VRL −0.3 to +6.5 −0.3 to +6.5 V V VSS differential voltage |VSS−VSSA| 0.1 V VDD differential voltage VDD−VDDA VDDA−VDD 6.5 0.3 V V Reference to supply differential voltage VDDA−VRH VRH−VDDA VDDA−VRL VRL−VDDA 6.5 0.3 6.5 0.3 V VDDA−VINDC VINDC−VDDA 6.5 0.3 V Analog input differential voltage . Table 20-9.
Electrical Specifications Table 20-10. Flash EEPROM Characteristics VDD = 5.
Electrical Specifications Tables of Data Table 20-12. Control Timing Characteristic Symbol 8.0 MHz Unit Min Max fo 0.004 8.0 MHz ECLK period tcyc 0.125 250 µs External oscillator frequency feo 0.5 16.0(1) MHz Processor control setup time tPCSU = tcyc/2 + 20 tPCSU 82.
Electrical Specifications PT[7:0]1 PWTIM PT[7:0] 2 PT71 PWPA PT72 NOTES: 1. Rising edge sensitive input 2. Falling edge sensitive input Figure 20-1. Timer Inputs Technical Data 414 MC68HC912D60A — Rev. 3.
Freescale Semiconductor MC68HC912D60A — Rev. 3.1 Electrical Specifications FFFE 4098 tcyc NOTE: Reset timing is subject to change. INTERNAL ADDRESS MODA, MODB RESET ECLK EXTAL VDD FFFE FREE 1ST PIPE 2ND PIPE 3RD PIPE tPCSU 1ST EXEC FFFE FFFE tMPS PWRSTL FFFE FREE tMPH 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Electrical Specifications Tables of Data Figure 20-2.
Technical Data Electrical Specifications SP-8 SP-8 SP-6 SP-6 SP-9 SP-9 PWIRQ tSTOPDELAY3 NOTES: 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 tcyc if DLY = 0. 4. XIRQ with X bit in CCR = 1. 5. IRQ or (XIRQ with X bit in CCR = 0).
Freescale Semiconductor MC68HC912D60A — Rev. 3.1 Electrical Specifications SP – 2 NOTE: RESET also causes recovery from WAIT. R/W ADDRESS IRQ, XIRQ, OR INTERNAL INTERRUPTS ECLK SP – 6 . . . SP – 9 PC, IY, IX, B:A, , CCR STACK REGISTERS SP – 4 SP – 9 SP – 9 . . . SP – 9 SP – 9 tPCSU VECTOR ADDRESS tWRS FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Electrical Specifications Tables of Data Figure 20-4.
VECT DATA Technical Data Electrical Specifications NOTES: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) R/W VECTOR ADDR PWIRQ tPCSU ADDRESS IRQ2, XIRQ, OR INTERNAL INTERRUPT IRQ1 ECLK PC SP – 2 PROG FETCH 1ST PIPE IY SP – 4 IX SP – 6 PROG FETCH 2ND PIPE B:A SP – 8 CCR SP – 9 PROG FETCH 3RD PIPE 1ST EXEC Electrical Specifications Figure 20-5. Interrupt Timing Diagram MC68HC912D60A — Rev. 3.
Electrical Specifications Tables of Data Table 20-13. Peripheral Port Timing Characteristic Symbol 8.0 MHz Unit Min Max fo 0.004 8.0 MHz tcyc 0.
Electrical Specifications Table 20-14. Multiplexed Expansion Bus Timing VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic(1), (2), (3), (4) Num Delay Symbol Frequency of operation (ECLK frequency) 8 MHz Min Max Unit fo 0.004 8.0 MHz 0.
Electrical Specifications Tables of Data 1 2 3 ECLK 16 17 18 19 20 21 R/W LSTRB (W/O TAG ENABLED) 5 23 7 11 22 10 12 ADDRESS READ ADDRESS/DATA MULTIPLEXED DATA 9 8 13 ADDRESS WRITE 15 14 DATA 24 25 26 DBE NOTE: Measurement points shown are 20% and 70% of VDD Figure 20-8. Multiplexed Expansion Bus Timing Diagram MC68HC912D60A — Rev. 3.
Electrical Specifications Table 20-15. SPI Timing (VDD = 5.
Electrical Specifications Tables of Data SS1 (OUTPUT) 5 2 1 SCK (CPOL = 0) (OUTPUT) 3 12 4 4 13 SCK (CPOL = 1) (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . 10 . . 1 LSB IN 10 MOSI (OUTPUT) 11 BIT 6 . MSB OUT2 . . 1 LSB OUT 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. A) SPI Master Timing (CPHA = 0) SS1 (OUTPUT) 5 1 2 13 12 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 4 6 MISO (INPUT) 7 MSB IN2 . .
Electrical Specifications SS (INPUT) 5 1 13 12 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 9 8 MISO (OUTPUT) 10 6 MOSI (INPUT) 11 BIT 6 . MSB OUT SLAVE 11 . . 1 . . 1 SEE NOTE SLAVE LSB OUT 7 BIT 6 . MSB IN LSB IN NOTE: Not defined but normally MSB of character just received.
Electrical Specifications Tables of Data Table 20-16. CGM Characteristics VDD = 5.0 V dc ±10%, VSS = 0 V dc, TA = TL to TH Characteristic Symbol Min. PLL reference frequency fREF Bus frequency VCO range Max. Unit 0.5 8 MHz fBUS 0.004 8 MHz fVCO 2.5 8 MHz fVCOMIN 0.5 2.5(1) MHz ∆trk 3% 4% — ∆Lock 0% 1.5% — Un-Lock Detection ∆unl 0.5% 2.
Electrical Specifications Table 20-18. Key Wake-up VDD = 5.0V dc ± 10%, VSS = 0 Vdc, TA = TL to TH Characteristic STOP Key Wake-Up Filter time Key Wake-Up Single Pulse Time Interval Symbol tKWSTP Min. 2 tKWSP 20 Max. 10 Unit µs µs Table 20-19. msCAN12 Wake-up Time from Sleep Mode VDD = 5.0V dc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic Wake-Up time Symbol twup Technical Data 426 Min. 2 Max. 5 Unit µs MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Section 21. Appendix: CGM Practical Aspects 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 21.3 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . . 427 21.4 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . . 433 21.2 Introduction This sections provides useful and practical pieces of information concerning the implementation of the CGM module. 21.
Appendix: CGM Practical Aspects synchronizers would be jeopardized (e.g. the MCLK and XCLK clock generators). 21.3.2 Operation Under Adverse Environmental Conditions The normal operation for the PLL is the so-called ‘automatic bandwidth selection mode’ which is obtained by having the AUTO bit set in the PLLCR register.
Appendix: CGM Practical Aspects Practical Aspects For The PLL Usage acquisition (AUTO=0, ACQ=0 in the PLLCR register). In both equations, the power supply should be 5V. Start with the target loop bandwidth as a function of the other parameters, but obviously, nothing prevents the user from starting with the capacitor value for example. Also, remember that the smoothing capacitor is always assumed to be one tenth of the series capacitance value.
Appendix: CGM Practical Aspects The filter components values are chosen from standard series (e.g. E12 for resistors). The operating voltage is assumed to be 5V (although there is only a minor difference between 3V and 5V operation). The smoothing capacitor Cp in parallel with R and C is set to be 1/10 of the value of C. The reference frequencies mentioned in this table correspond to the output of the fine granularity divider controlled by the REFDV register.
Appendix: CGM Practical Aspects Practical Aspects For The PLL Usage Table 21-1. Suggested 8MHz Synthesis PLL Filter Elements (Tracking Mode) Reference [MHz] SYNR Fbus [MHz] C [nF] R [kΩ] Loop Bandwidth [kHz] Bandwidth Limit [kHz] 0.614 $0C 7.98 100 4.3 1.1 157 0.614 $0C 7.98 4.7 20 5.3 157 0.614 $0C 7.98 1 43 11.5 157 0.614 $0C 7.98 0.33 75 20 157 0.8 $09 8.00 220 2.7 0.9 201 0.8 $09 8.00 10 12 4.2 201 0.8 $09 8.00 2.2 27 8.6 201 0.8 $09 8.00 0.
Appendix: CGM Practical Aspects Table 21-2. Suggested 8MHz Synthesis PLL Filter Elements (Acquisition Mode) Reference [MHz] SYNR Fbus [MHz] C [nF] R [kΩ] Loop Bandwidth [kHz] Bandwidth Limit [kHz] 0.614 $0C 7.98 1000 0.43 1.2 157 0.614 $0C 7.98 47 2 5.5 157 0.614 $0C 7.98 10 4.3 12 157 0.614 $0C 7.98 3.3 7.5 21 157 0.8 $09 8.00 2200 0.27 0.9 201 0.8 $09 8.00 100 1.2 4.4 201 0.8 $09 8.00 22 2.4 9.3 201 0.8 $09 8.00 4.7 5.6 20.1 201 1 $07 8.
Appendix: CGM Practical Aspects Printed Circuit Board Guidelines 21.4 Printed Circuit Board Guidelines Printed Circuit Boards (PCBs) are the board of choice for volume applications. If designed correctly, a very low noise system can be built on a PCB with consequently good EMI/EMC performances. If designed incorrectly, PCBs can be extremely noisy and sensitive modules, and the CGM could be disrupted. Some common sense rules can be used to prevent such problems.
Appendix: CGM Practical Aspects spectrum. This is especially the case for the power supply pins close to the E port, when the ECLK and/or the calibration clock are used. • On the general VDD power supply input, a ‘T’ low pass filter LCL can be used (e.g. 10µH-47µF-10µH). The ‘T’ is preferable to the ‘Π’ version as the exhibited impedance is more constant with respect to the VDD current.
Appendix: CGM Practical Aspects Printed Circuit Board Guidelines In addition to the above general pieces of advice, the following guidelines should be followed for the CGM pins (but also more generally for any sensitive analog circuitry): • Parasitic capacitance on EXTAL is absolutely critical – probably the most critical layout consideration. The XTAL pin is not as sensitive. All routing from the EXTAL pin through the resonator and the blocking cap to the actual connection to VSS must be considered.
Appendix: CGM Practical Aspects • Mount the PLL filter and oscillator components as close to the MCU as possible. • Do not allow the EXTAL and XTAL signals to interfere with the XFC node. Keep these tracks as short as possible. • Do not cross the CGM signals with any other signal on any level. • Remember that the reference voltage for the XFC filter is VDDPLL.
Technical Data — MC68HC912D60A Section 22. Appendix: Changes from MC68HC912D60 22.1 Contents 22.2 Significant changes from the MC68HC912D60 (non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 22.2.1 Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 22.2.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 22.2.3 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix: Changes from MC68HC912D60 22.2.1.3 Flash Programming Procedure Programming of the flash is greatly simplified over previous HC12s. The read / verify / re-pulse programming algorithm is replaced by a much simpler method. 22.2.1.4 Flash Programming Time The most significant change resulting from the new flash technology is that the bulk erase and program times are now fixed. The erase time is at least twice as fast while the word programming time is at least 20% faster. 22.2.1.
Appendix: Changes from MC68HC912D60 Significant changes from the MC68HC912D60 (non-suffix device) to be set by programming an 10-bit time base pre-scalar into bits spread over two new registers, EEDIVH and EEDIVL. The EEDIVH and EEDIVL registers are volatile. However, they are loaded upon reset by the contents of the non-volatile SHADOW word much in the same way as the EEPROM module control register (EEMCR) bits interact with the SHADOW word for configuration control on the existing revision. 22.2.2.
Appendix: Changes from MC68HC912D60 22.2.4 WAIT mode This new version will correctly exit WAIT mode using short XIRQ or IRQ inputs. 22.2.5 KWU Filter The KWU filter will now ignore pulses shorter than 2 microseconds. 22.2.6 Port ADx Power must be applied to VDDA at all times even if the ADC is not being used. This is necessary for port AD0 and port AD1 to function correctly as digital inputs. This is also valid for MC68HC912D60. 22.2.7 ATD 22.2.7.
Appendix: Changes from MC68HC912D60 Significant changes from the MC68HC912D60 (non-suffix device) 22.2.7.3 Additional Features ATD flexibility has been increased with additional signed result, data justification, single conversion selection and results location FIFO features. The DJM bit has been added to ATDxCTL2 register. Default values are compatible with MC68HC912D60 functionality. FIFO & S1C bits have been added to ATDxCTL3 register. Default values are compatible with MC68HC912D60 functionality. 22.2.
Appendix: Changes from MC68HC912D60 To ensure compatibility, the application should not rely on ongoing conversions being aborted. Also any interrupts from the completion of an ongoing sequence should be masked and/or handled correctly. 22.2.7.7 SCF bit In SCAN mode (SCAN bit = 1 in ATDxCTL5) the Sequence Complete Flag (SCF bit in ATDSTATx) is set after completion of each conversion sequence. Previously it was only set at the end of the first conversion sequence.
Technical Data — MC68HC912D60A Section 23. Appendix: Information on MC68HC912D60A Mask Set Changes 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.3 Flash Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 23.4 Clock Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 23.5 Pseudo Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 23.
Appendix: Information on MC68HC912D60A Mask 23.4 Clock Circuitry The crystal oscillator output is now frozen when Limp Home (LH) mode is entered to prevent rapid switching between crystal and LH clocks. Improvements have been made to the bus clock switching circuitry to eliminate the potential for glitches to appear on the internal clock line. The duration of the clock monitor pulses was increased to reduce sensitivity of the clock monitor circuit to short clock pulses. 23.
Appendix: Information on MC68HC912D60A Mask Set Changes PLL 23.7 PLL The limp Home clock frequency has been re-alligned to the specification values to reduce sensitivity to system noise and hence reduce PLL jitter. Note: It is advisable to verify the XFC filter components and PLL lock time due to the above changes. VCO start-up will now be at the minimum frequency whilst the power up sequence of the current controlled oscillator has been improved.
Appendix: Information on MC68HC912D60A Mask Technical Data 446 MC68HC912D60A — Rev. 3.
Technical Data — MC68HC912D60A Glossary A — See “accumulators (A and B or D).” accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers in the CPU. The CPU uses the accumulators to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation with large loop bandwidth. Also see ’tracking mode’. address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
Glossary binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example, 234 (decimal) = 0010 0011 0100 (BCD) bit — A binary digit. A bit has a value of either logic 0 or logic 1. branch instruction — An instruction that causes the CPU to continue processing at a memory location other than the next sequential address.
Glossary computer operating properly module (COP) — A counter module that resets the MCU if allowed to overflow. condition code register (CCR) — An 8-bit register in the CPU that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit — One bit of a register manipulated by software to control the operation of the module. control unit — One of two major units of the CPU.
Glossary cycle time — The period of the operating frequency: tCYC = 1/fOP. D — See “accumulators (A and B or D).” decimal number system — Base 10 numbering system that uses the digits zero through nine. duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually represented by a percentage. ECT — See “enhanced capture timer.” EEPROM — Electrically erasable, programmable, read-only memory.
Glossary input/output (I/O) — Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions — Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction.
Glossary memory location — Each M68HC12 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus.
Glossary operand — Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator — A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed.
Glossary program counter (PC) — A 16-bit register in the CPU. The PC register holds the address of the next instruction or operand that the CPU will use. pull — An instruction that copies into the accumulator the contents of a stack RAM location. The stack RAM address is in the stack pointer. pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width — The amount of time a signal is on as opposed to being in its off state.
Glossary shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed — A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number.
Glossary two’s complement — A means of performing binary subtraction using addition techniques. The most significant bit of a two’s complement number indicates the sign of the number (1 indicates negative). The two’s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered — Utilizes only one register for data; new data overwrites current data. unimplemented memory location — A memory location that is not used.
Technical Data — MC68HC912D60A Revision History 23.8 Contents 23.9 Changes from Rev 2.0 to Rev 3.0 . . . . . . . . . . . . . . . . . . . . . 457 23.10 Major Changes From Rev 1.0 to Rev 2.0 . . . . . . . . . . . . . . . . 457 23.11 Major Changes From Rev 0.0 to Rev 1.0 . . . . . . . . . . . . . . . . 458 23.9 Changes from Rev 2.0 to Rev 3.0 Section Page (in Rev 3.0) EEPROM 110 Description of change Note referring to bit 6 of SHADOW word has been modified. 23.10 Major Changes From Rev 1.0 to Rev 2.
Revision History Section Page (in Rev 2.
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