Datasheet

EEPROM Memory
Technical Data MC68HC912D60A — Rev. 3.1
108 EEPROM Memory Freescale Semiconductor
A steady internal self-time clock is required to provide accurate counts
to meet EEPROM program/erase requirements. This clock is generated
via a programmable 10-bit prescaler register. Automatic program/erase
termination is also provided.
In ordinary situations, with crystal operating properly, the steady internal
self-time clock is derived from the input clock source (EXTALi). The
divider value is as in EEDIVH:EEDIVL. In limp-home mode, where the
oscillator clock has malfunctioned or is unavailable, the self-time clock is
derived from the PLL at a nominal f
VCOMIN
using a predefined divider
value of $0023. Program/erase operation is not guaranteed in limp-
home mode.
CAUTION: It is strongly recommended that program/erase operation is terminated
in the event of loss of crystal, either by the application software (clearing
EEPGM & EELAT bits) when entering limp home mode or by enabling
the clock monitor to generate a clock monitor reset. This will prevent
unnecessary stress on the emulated EEPROM during oscillator failure.
8.5 EEPROM Control Registers
EEDIVH — EEPROM Modulus Divider $00EE
Bit 7654321Bit 0
000000EEDIV9EEDIV8
RESET: 000000—
(1)
—
(1)
1. Loaded from SHADOW word.
EEDIVL — EEPROM Modulus Divider $00EF
Bit 7654321Bit 0
EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
RESET: —
(1)
—
(1)
—
(1)
—
(1)
—
(1)
—
(1)
—
(1)
—
(1)
1. Loaded from SHADOW word.