Datasheet

I/O Ports with Key Wake-up
Technical Data MC68HC912D60A — Rev. 3.1
130 I/O Ports with Key Wake-up Freescale Semiconductor
Pull-up/down status is selected by PGUPD and PHUPD input pins: pull-
up when PxUPD pin is high, pull-down when PxUPD pin is low. On
80QFP these pins are tied internally so that KWG4 is pull-up and KWH4
is pull-down.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to Operating Modes and Resource Mapping.
10.3 Key Wake-up and Port Registers
Read and write anytime.
Read and write anytime.
Bit 7654321Bit 0
PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
RESET:————————
Alt. Pin
Function
— KWG6 KWG5 KWG4 KWG3 KWG2 KWG1 KWG0
PORTG — Port G Register $0028
Bit 7654321Bit 0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
RESET: — — — — — — — —
Alt. Pin
Function
KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0
PORTH — Port H Register $0029