Datasheet

I/O Ports with Key Wake-up
Technical Data MC68HC912D60A — Rev. 3.1
132 I/O Ports with Key Wake-up Freescale Semiconductor
Read and write anytime.
WI2CE — Wake-up I
2
C Enable
0 = PG6 default key wake-up on falling edge
1 = I
2
C Start condition detection on PG7 and PG6
When WI2CE is set, PG6 and PG7 operate in wired-OR or open-drain
mode.
The I
2
C Start condition is defined as a high to low transition of the
SDA line when SCL is high. When WI2CE is set, a falling edge on
PG6 (SDA) is recognized only if PG7 (SCL) is high.
Depending on WI2CE bit, KWIEG6 enables either falling edge or I
2
C
Start condition interrupt.
KWIEG[6:0] — Key Wake-up Port G Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
Read and write anytime.
KWIEH[7:0] — Key Wake-up Port H Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
Bit 7654321Bit 0
WI2CE KWIEG6 KWIEG5 KWIEG4 KWIEG3 KWIEG2 KWIEG1 KWIEG0
RESET:00000000
KWIEG — Key Wake-up Port G Interrupt Enable Register $002C
Bit 7654321Bit 0
KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0
RESET: 0 0 0 0 0 0 0 0
KWIEH — Key Wake-up Port H Interrupt Enable Register $002D