Datasheet

Clock Functions
Technical Data MC68HC912D60A — Rev. 3.1
140 Clock Functions Freescale Semiconductor
Figure 11-2. PLL Functional Diagram
The PLL may be used to run the MCU from a different time base than the
incoming crystal value. It creates an integer multiple of a reference
frequency. For increased flexibility, the crystal clock can be divided by
values in a range of 1 – 8 (in unit steps) to generate the reference
frequency. The PLL can multiply this reference clock in a range of 1 to
64. Although it is possible to set the divider to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If the PLL is selected, it will continue to run when in WAIT mode resulting
in more power consumption than normal. To take full advantage of the
reduced power consumption of WAIT mode, turn off the PLL before
going into WAIT. Please note that in this case the PLL stabilization time
applies.
The PLL operation is suspended in STOP mode. After STOP exit
followed by the stabilization time, it resumes operation at the same
frequency, provided the AUTO bit is set.
A passive external loop filter must be placed on the control line (XFC
pad). The filter is a second-order, low-pass filter to eliminate the VCO
input ripple. Values of components in the diagram are dependent upon
the desired VCO operation. See XFC description.
REDUCED
CONSUMPTION
OSCILLATOR
EXTAL
XTAL
EXTALi
PLLCLK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
REFDV <2:0>
LOOP
PROGRAMMABLE
DIVIDER
SYN <5:0>
CPUMP VCO
LOCK
LOOP
FILTER
XFC
PAD
UP
DOWN
LOCK
DETECTOR
REFCLK
DIVCLK
SLOW MODE
PROGRAMMABLE
CLOCK DIVIDER
SLDV <5:0>
XCLK
EXTALi
÷2
SLWCLK
VDDPLL
× 2