Datasheet

MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Figures 15
Technical Data — MC68HC912D60A
List of Figures
Figure Title Page
1-1 MC68HC912D60A 112-pin QFP Block Diagram . . . . . . . . . . .29
1-2 MC68HC912D60A 80-pin QFP Block Diagram . . . . . . . . . . . .30
2-1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3-1 Pin Assignments in 112-pin TQFP for MC68HC912D60A . . . .38
3-2 112-pin TQFP Mechanical Dimensions (case no987) . . . . . . .39
3-3 Pin Assignments in 80-pin QFP for MC68HC912D60A . . . . . .40
3-4 80-pin QFP Mechanical Dimensions (case no841B) . . . . . . . .41
3-5 PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .43
3-6 External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .45
5-1 MC68HC912D60A Memory Map . . . . . . . . . . . . . . . . . . . . . . .83
6-1 Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .86
10-1 STOP Key Wake-up Filter (falling edge trigger) timing. . . . . .135
11-1 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .139
11-2 PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .144
11-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .146
11-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .149
11-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .164
11-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
11-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .166
12-1 MC68HC912D60A Colpitts Oscillator Architecture. . . . . . . . .177
12-2 MC68HC912D60C Colpitts Oscillator Architecture. . . . . . . . .180
12-3 MC68HC912D60C Crystal with DC Blocking Capacitor. . . . .192
12-4 MC68HC912D60P Pierce Oscillator Architecture. . . . . . . . . .195
13-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .208
13-2 Block Diagram of PWM Center-Aligned Output Channel . . . .209
13-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
14-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .225
14-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .226