Datasheet

Clock Functions
Technical Data MC68HC912D60A — Rev. 3.1
156 Clock Functions Freescale Semiconductor
11.6.15 PLL Register Descriptions
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Always reads zero, except in test modes.
Bit 7654321Bit 0
0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
RESET: 00000000
SYNR — Synthesizer Register $0038
Bit 7654321Bit 0
00000REFDV2REFDV1REFDV0
RESET: 0 0 0 0 0 0 0 0
REFDV — Reference Divider Register $0039
Bit 7654321Bit 0
TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0
RESET: 0 0 0 0 0 0 0 0
CGTFLG — Clock Generator Test Register $003A