Datasheet

Clock Functions
Clock Divider Chains
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Clock Functions 163
Figure 11-6. Clock Generation Chain
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
REDUCED
CONSUMPTION
OSCILLATOR
PHASE
LOCK
LOOP
EXTAL
XTAL
0:0
SYSCLK
TO
BUSES,
SPI,
PWM,
ATD0, ATD1
TO
RTI, COP
BCSP BCSS
SLOW MODE
CLOCK
DIVIDER
EXTALi
EXTALi
EXTALi
SLWCLK
PLLCLK
0:1
BCSP BCSS
1:x
BCSP BCSS
MCS = 0
MCS = 1
÷ 2
÷2
TO
MSCAN
CLKSRC = 1
TCLKs
T CLOCK
GENERATOR
E AND P
CLOCK
GENERATOR
PCLK
ECLK
XCLK
TO
SCI0, SCI1,
ECT
TO CPU
SYNC
MCLK
TO BDM
÷ 2
SYNC
TO CAL
TO CLOCK
MONITOR
CLKSRC = 0
CLKSW = 0
CLKSW = 1
BDMCLK