Datasheet

Clock Functions
Clock Divider Chains
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Clock Functions 165
Figure 11-8. Clock Chain for ECT
BITS: PR2, PR1, PR0
MCLK
PAMOD
PACLK
PULSE ACC
LOW BYTE
PACLK/256
PULSE ACC
HIGH BYTE
PACLK/65536
(PAOV)
GATE
LOGIC
BITS: PAEN, CLK1, CLK0
TEN
REGISTER: PACTL
REGISTER: TMSK2
PAEN
0:0:0
0:0:1
÷ 2
0:1:0
÷ 2
0:1:1
÷ 2
1:0:0
÷ 2
1:0:1
÷ 2
1:1:0
÷ 2
1:1:1
÷ 2
BITS: MCPR1, MCPR0
MCEN
REGISTER: MCCTL
0:0
0:1
÷ 4
1:0
÷ 2
1:1
÷ 2
0:x:x
1:0:0
1:0:1
1:1:0
1:1:1
TO TIMER
MAIN
COUNTER
(TCNT)
MODULUS
DOWN
COUNTER
PORT T7
Prescaled MCLK