Datasheet

Clock Functions
Technical Data MC68HC912D60A — Rev. 3.1
172 Clock Functions Freescale Semiconductor
DISR — Disable Resets from COP Watchdog and Clock Monitor
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor
will not generate a system reset.
CR2, CR1, CR0 — COP Watchdog Timer Rate select bits
These bits select the COP time-out rate. The clock used for this
module is the XCLK.
Write once in normal modes, anytime in special modes. Read
anytime.
Table 11-5. COP Watchdog Rates
CR2 CR1 CR0
Divide
X clock
by
8.0 MHz X clock.
Time-out
Window COP enabled:
Window start
(1)
Window end
Effective
Window
(2)
0 0 0 OFF OFF OFF OFF OFF
001
2
13
1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms
0%
(3)
010
2
15
4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 %
011
2
17
16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.4 %
100
2
19
65.536 ms -0/+1.024 ms 49.152 ms 64.512 ms 23.4 %
101
2
21
262.144 ms -0/+1.024 ms 196.608 ms 261.120 ms 24.6 %
110
2
22
524.288 ms -0/+1.024 ms 393.216 ms 523.264 ms 24.8 %
111
2
23
1.048576 ms -0/+1.024 ms 786.432 ms 1.047552 s 24.9 %
1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.
2. Please refer to WCOP bit description above.
3. Window COP cannot be used at this rate.