Datasheet

MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Tables 19
Technical Data — MC68HC912D60A
List of Tables
Table Title Page
1-1 Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27
1-2 Development Tools Ordering Information. . . . . . . . . . . . . . . . .28
2-1 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .34
2-2 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .35
3-1 MC68HC912D60A Power and Ground Connection Summary .44
3-2 MC68HC912D60A Signal Description Summary . . . . . . . . . . .50
3-3 MC68HC912D60A Port Description Summary. . . . . . . . . . . . .59
3-4 Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .60
4-1 MC68HC912D60A Register Map . . . . . . . . . . . . . . . . . . . . . . .62
5-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5-2 Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
5-3 RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .82
5-4 EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .82
8-1 EEDIV Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8-2 1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .112
8-3 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8-4 Shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9-1 Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9-2 Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .128
11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .155
11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .155
11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .212
13-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . .222
13-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .222
14-1 Compare Result Output Action. . . . . . . . . . . . . . . . . . . . . . . .238
14-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .238