Datasheet

Pulse Width Modulator
Introduction
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Pulse Width Modulator 209
Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel
GATE
PWCNTx
8-BIT COMPARE =
PWDTYx
8-BIT COMPARE =
PWPERx
RESET
FROM PORT P
DATA REGISTER
TO PIN
DRIVER
PPOLx
CLOCK SOURCE
(ECLK or Scaled ECLK)
(CLOCK EDGE SYNC)
UP/DOWN
CENTR = 1
MUX
MUX
T
Q
Q
PWDTY
PWENx
PPOL = 1
PPOL = 0
(DUTY CYCLE)
(PERIOD)
PWPER
× 2
(PWPER − PWDTY) × 2
PWDTY
SYNC