Datasheet

Pulse Width Modulator
PWM Register Description
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Pulse Width Modulator 221
PORTP can be read anytime.
PWM functions share port P pins 3 to 0 and take precedence over the
general-purpose port when enabled.
When configured as input, a read will return the pin level.
When configured as output, a read will return the latched output data.
A write will drive associated pins only if configured for output and the
corresponding PWM channel is not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
DDRP determines pin direction of port P when used for general-purpose
I/O.
Read and write anytime.
DDRP[7:0] — Data Direction Port P pin 7-0
0 = I/O pin configured as high impedance input
1 = I/O pin configured for output.
Bit 7654321Bit 0
PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
PWM – – – – PWM3 PWM2 PWM1 PWM0
RESET:––––––––
PORTP — Port P Data Register $0056
Bit 7654321Bit 0
DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0
RESET:00000000
DDRP — Port P Data Direction Register $0057