Datasheet

Enhanced Capture Timer
Introduction
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 225
Figure 14-1. Timer Block Diagram in Latch Mode
16 BIT MAIN TIMER
PT1
Comparator
TC0H hold register
PT0
PT3
PT2
PT4
PT5
PT6
PT7
EDG0
EDG1
EDG2
EDG3
MUX
Prescaler
M clock
16-bit load register
16-bit modulus
0
RESET
EDG0
EDG1
EDG2
EDG4
EDG5
EDG3
EDG6
EDG7
÷ 1, 2, ..., 128
÷ 1, 4, 8, 16
16-bit Free-running
LATCH
Underflow
main timer
Prescaler
TC0 capture/compare register
Comparator
TC1 capture/compare register
Comparator
TC2 capture/compare register
Comparator
TC3 capture/compare register
Comparator
TC4 capture/compare register
Comparator
TC5 capture/compare register
Comparator
TC6 capture/compare register
Comparator
TC7 capture/compare register
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Delay counter
Delay counter
Delay counter
Delay counter
M clock
TC1H hold register
TC2H hold register
TC3H hold register
MUX
MUX
MUX
PA0H hold register
PAC0
0
RESET
PA1H hold register
PAC1
0
RESET
PA2H hold register
PAC2
0
RESET
PA3H hold register
PAC3
Write $0000
to modulus counter
ICLAT, LATQ, BUFEN
(force latch)
LATQ
(MDC latch enable)
down counter