Datasheet

Enhanced Capture Timer
Introduction
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 227
Figure 14-3. 8-Bit Pulse Accumulators Block Diagram
Host CPU data bus
PT0
Load holding register and reset pulse accumulator
0
0
EDG3
EDG2
EDG1
EDG0
Edge detector Delay counter
Interrupt
Interrupt
PT1
Edge detector Delay counter
PT2
Edge detector Delay counter
PT3
Edge detector Delay counter
8-bit PAC0 (PACN0)
PA0H holding register
0
8-bit PAC1 (PACN1)
PA1H holding register
0
8-bit PAC2 (PACN2)
PA2H holding register
0
8-bit PAC3 (PACN3)
PA3H holding register