Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
228 Enhanced Capture Timer Freescale Semiconductor
Figure 14-4. 16-Bit Pulse Accumulators Block Diagram
Edge detector
8-bit PAC2
Intermodule Bus
8-bit PAC3
PT7
PT0
M clock
Divide by 64
Clock select
CLK0
CLK1
4:1 MUX
To TCNT Counter
PACLK PACLK / 256 PACLK / 65536
Prescaled MCLK
(TMSK2 bits PR2-PR0)
Interrupt
MUX
(PAMOD)
Edge detector
PACA
Delay counter
(PACN3) (PACN2)
8-bit PAC08-bit PAC1
Interrupt
PACB
(PACN1) (PACN0)