Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
234 Enhanced Capture Timer Freescale Semiconductor
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7-0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding IOSn bit is set to be an output compare. This does not
change the state of the DDRT bits. At successful OC7, for each bit that
is set in OC7M, the corresponding data bit OC7D is stored to the
corresponding bit of the timer port.
NOTE: OC7M has priority over output action on the timer port enabled by OMn
and OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the
action of corresponding OM and OL bits on the selected timer port.
Bit 7654321Bit 0
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
RESET: 0 0 0 0 0 0 0 0
CFORC — Timer Compare Force Register $0081
Bit 7654321Bit 0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
RESET: 0 0 0 0 0 0 0 0
OC7M — Output Compare 7 Mask Register $0082