Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
238 Enhanced Capture Timer Freescale Semiconductor
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
Table 14-1. Compare Result Output Action
OMn OLn Action
0 0 Timer disconnected from output pin logic
0 1 Toggle OCn output line
1 0 Clear OCn output line to zero
1 1 Set OCn output line to one
Bit 7654321Bit 0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
RESET: 0 0 0 0 0 0 0 0
TCTL3 — Timer Control Register 3 $008A
Bit 7654321Bit 0
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
RESET:00000000
TCTL4 — Timer Control Register 4 $008B
Table 14-2. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)