Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
240 Enhanced Capture Timer Freescale Semiconductor
RDPT — Timer Port Drive Reduction
This bit reduces the effective output driver size which can reduce
power supply current and generated noise depending upon pin
loading.
0 = Normal output drive capability
1 = Enable output drive reduction function
TCRE — Timer Counter Reset Enable
This bit allows the timer counter to be reset by a successful output
compare 7 event. This mode of operation is similar to an up-counting
modulus counter.
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is
reset from $FFFF to $0000.
PR2, PR1, PR0 — Timer Prescaler Select
These three bits specify the number of ÷2 stages that are to be
inserted between the module clock and the main timer counter.
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
Table 14-3. Prescaler Selection
PR2 PR1 PR0
Prescale
Factor
000 1
001 2
010 4
011 8
100 16
101 32
110 64
1 1 1 128