Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
242 Enhanced Capture Timer Freescale Semiconductor
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC0 — Timer Input Capture/Output Compare Register 0 $0090–$0091
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC1 — Timer Input Capture/Output Compare Register 1 $0092–$0093
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC2 — Timer Input Capture/Output Compare Register 2 $0094–$0095
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC3 — Timer Input Capture/Output Compare Register 3 $0096–$0097
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC4 — Timer Input Capture/Output Compare Register 4 $0098–$0099
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC5 — Timer Input Capture/Output Compare Register 5 $009A–$009B