Datasheet

Enhanced Capture Timer
Timer Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 243
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All
timer input capture/output compare registers are reset to $0000.
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
Read: any time
Write: any time
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC6 — Timer Input Capture/Output Compare Register 6 $009C–$009D
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TC7 — Timer Input Capture/Output Compare Register 7 $009E–$009F
BIT 7654321BIT 0
0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
RESET: 00000000
PACTL — 16-Bit Pulse Accumulator A Control Register $00A0