Datasheet

Enhanced Capture Timer
Timer Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 245
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the E÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Bits
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator A Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
Read or write anytime. When the TFFCA bit in the TSCR register is set,
any access to the PACNT register will clear all the flags in the PAFLG
register.
PAOVF — Pulse Accumulator A Overflow Flag
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
CLK1 CLK0 Clock Source
0 0 Use timer prescaler clock as timer counter clock
0 1 Use PACLK as input to timer counter clock
1 0 Use PACLK/256 as timer counter clock frequency
1 1 Use PACLK/65536 as timer counter clock frequency
BIT 7654321BIT 0
000000PAOVFPAIF
RESET: 00000000
PAFLG — Pulse Accumulator A Flag Register $00A1