Datasheet

Enhanced Capture Timer
Timer Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 247
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read: any time
Write: any time
MCZI — Modulus Counter Underflow Interrupt Enable
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
BIT 7654321BIT 0
$00A4BIt 7654321Bit 0PACN1 (hi)
$00A5Bit 7654321Bit 0PACN0 (lo)
RESET:00000000
PACN1, PACN0 — Pulse Accumulators Count Registers $00A4, $00A5
BIT 7654321BIT 0
MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0
RESET: 00000000
MCCTL — 16-Bit Modulus Down-Counter Control Register $00A6