Datasheet

Enhanced Capture Timer
Timer Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 249
MCEN — Modulus Down-Counter Enable
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
MCPR1, MCPR0 — Modulus Counter Prescaler select
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
The flag is set when the modulus down-counter reaches $0000.
Writing a1 to this bit clears the flag (if TFFCA=0). Writing zero has no
effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
MCPR1 MCPR0
Prescaler division
rate
00 1
01 4
10 8
11 16
BIT 7654321BIT 0
MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0
RESET: 0 0 0 0 0 0 0 0
MCFLG — 16-Bit Modulus Down-Counter FLAG Register $00A7