Datasheet

Enhanced Capture Timer
Timer Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Enhanced Capture Timer 251
Read: any time
Write: any time
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
Read: any time
Write: any time
BIT 7654321BIT 0
000000DLY1DLY0
RESET: 0 0 0 0 0 0 0 0
DLYCT — Delay Counter Control Register $00A9
DLY1 DLY0 Delay
0 0 Disabled (bypassed)
0 1 256 M clock cycles
1 0 512 M clock cycles
1 1 1024 M clock cycles
BIT 7654321BIT 0
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
RESET:00000000
ICOVW — Input Control Overwrite Register $00AA