Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
256 Enhanced Capture Timer Freescale Semiconductor
Read or write any time.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output.
The timer forces the I/O state to be an output for each timer port line
associated with an enabled output compare. In these cases the data
direction bits will not be changed, but have no effect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of
a pin when the associated timer output compare is disabled. Input
captures do not override the DDRT settings.
Read: any time
Write: any time
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input
pin with IC0.
PBEN — Pulse Accumulator B System Enable
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
PAC0 can be enabled when their related enable bits in
ICPACR ($A8) are set.
BIT 7654321BIT 0
DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0
RESET: 00000000
DDRT — Data Direction Register for Timer Port $00AF
BIT 7654321BIT 0
0 PBEN 0000PBOVI0
RESET: 00000000
PBCTL — 16-Bit Pulse Accumulator B Control Register $00B0