Datasheet

Enhanced Capture Timer
Technical Data MC68HC912D60A — Rev. 3.1
258 Enhanced Capture Timer Freescale Semiconductor
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see Pulse Accumulators).
Read: any time
Write: any time
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
BIT 7654321BIT 0
$00B2BIt 7654321Bit 0PA3H
$00B3Bit 7654321Bit 0PA2H
$00B4BIt 7654321Bit 0PA1H
$00B5Bit 7654321Bit 0PA0H
RESET:00000000
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers $00B2–$00B5
BIT 7654321BIT 0
$00B6 BIt 15 14 13 12 11 10 9 Bit 8 MCCNTH
$00B7 Bit 7 6 5 4 3 2 1 Bit 0 MCCNTL
RESET:11111111
MCCNTH/L — Modulus Down-Counter Count Register $00B6, $00B7