Datasheet

General Description
Technical Data MC68HC912D60A — Rev. 3.1
26 General Description Freescale Semiconductor
• Serial interfaces
– Two asynchronous serial communications interfaces (SCI)
– MI-Bus implemented on final devices
– Synchronous serial peripheral interface (SPI)
• LIM (light integration module)
– WCR (windowed COP watchdog, real time interrupt, clock
monitor)
– ROC (reset and clocks)
– MEBI (multiplexed external bus interface)
– MBI (internal bus interface and map)
– INT (interrupt control)
• Clock generation
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Slow mode divider
– Low power 0.5 to 16 MHz crystal oscillator reference clock
– Option of a Pierce or Colpitts oscillator
• 112-Pin TQFP package or 80-pin QFP package
– Up to 68 general-purpose I/O lines, plus up to 18 input-only
lines in 112TQFP
or
Up to 48 general-purpose I/O lines, plus up to 10 input-only
lines in 80QFP
• 8MHz operation at 5V
• Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints