Datasheet

Multiple Serial Interface
Technical Data MC68HC912D60A — Rev. 3.1
266 Multiple Serial Interface Freescale Semiconductor
15.4.1 Data Format
The serial data format requires the following conditions:
• An idle-line in the high state before transmission or reception of a
message.
• A start bit (logic zero), transmitted or received, that indicates the
start of each character.
• Data that is transmitted or received least significant bit (LSB) first.
• A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
• A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
• This SCI supports hardware parity for transmit and receive.
15.4.2 SCI Baud Rate Generation
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the M Clock.
Table 15-1. Baud Rate Generation
Desired
SCI Baud Rate
BR Divisor for
M = 4.0 MHz
BR Divisor for
M = 8.0 MHz
110 2273 4545
300 833 2273
600 417 833
1200 208 417
2400 104 208
4800 52 104
9600 26 52
14400 17 35
19200 13 26
38400 — 13