Datasheet

Multiple Serial Interface
Serial Peripheral Interface (SPI)
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Multiple Serial Interface 277
Figure 15-3. Serial Peripheral Interface Block Diagram
A clock phase control bit (CPHA) and a clock polarity control bit (CPOL)
in the SP0CR1 register select one of four possible clock formats to be
used by the SPI system. The CPOL bit simply selects non-inverted or
inverted clock. The CPHA bit is used to accommodate two
fundamentally different protocols by shifting the clock by one half cycle
or no phase shift.
PIN
CONTROL
LOGIC
8-BIT SHIFT REGISTER
READ DATA BUFFER
SHIFT CONTROL LOGIC
CLOCK
LOGIC
SPI CONTROL
SP0SR SPI STATUS REGISTER
SP0DR SPI DATA REGISTER
SPIF
WCOL MODF
DIVIDER
SELECT
SP0BR SPI BAUD RATE REGISTER
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256
SPI
INTERRUPT
INTERNAL BUS
MCU P CLOCK
(SAME AS E RATE)
S
M
M
S
M
S
SPR2 SPR1
SPR0
REQUEST
SPIE SPE MSTR CPOL CPHA LSBF
LSBF
PUPS RDS
SWOM
SPC0
SSOE
SPE
CLOCK
MSTR
SWOM
MISO
PS4
SCK
PS6
SS
PS7
MOSI
PS5
SP0CR1 SPI CONTROL REGISTER 1 SP0CR2 SPI CONTROL REGISTER 2