Datasheet

Multiple Serial Interface
Technical Data MC68HC912D60A — Rev. 3.1
278 Multiple Serial Interface Freescale Semiconductor
Figure 15-4. SPI Clock Format 0 (CPHA = 0)
t
L
Begin End
SCK (CPOL=0)
SAMPLE I
CHANGE O
SEL SS
(O)
Transfer
SCK (CPOL=1)
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
CHANGE O
SEL SS
(I)
(MOSI pin)
(MISO pin)
(Master only)
(MOSI/MISO)
t
T
If next transfer begins here
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L