Datasheet

Multiple Serial Interface
Technical Data MC68HC912D60A — Rev. 3.1
280 Multiple Serial Interface Freescale Semiconductor
15.5.4 Bidirectional Mode (MOMI or SISO)
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
15.5.5 Register Descriptions
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to Operating Modes
and Resource Mapping.
Read or write anytime.
When SPE=1 Master Mode
MSTR=1
Slave Mode
MSTR=0
Normal
Mode
SPC0=0
SWOM enables open drain output. SWOM enables open drain output.
Bidirectional
Mode
SPC0=1
SWOM enables open drain output. PS4 becomes GPIO. SWOM enables open drain output. PS5 becomes GPIO.
Figure 15-6. Normal Mode and Bidirectional Mode
SPI
MO
MI
DDS5
Serial Out
Serial In
SPI
SI
SO
Serial In
Serial Out
DDS4
SPI
MOMI
PS4
DDS5
Serial Out
Serial In
SPI
PS5
SISO
DDS4
Serial In
Serial Out
Bit 7654321Bit 0
SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF
RESET: 0 0 0 0 0 1 0 0
SP0CR1 — SPI Control Register 1 $00D0