Datasheet

Multiple Serial Interface
Technical Data MC68HC912D60A — Rev. 3.1
282 Multiple Serial Interface Freescale Semiconductor
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
Read or write anytime.
SPSWAI — Serial Interface Stop in WAIT mode
0 = Serial interface clock operates normally
1 = Halt serial interface clock generation in WAIT mode
SPC0 — Serial Pin Control 0
This bit decides serial pin configurations with MSTR control bit.
Bit 7654321Bit 0
0 0 0 0 0 0 SPSWAI SPC0
RESET: 0 0 0 0 0 0 0 0
SP0CR2 — SPI Control Register 2 $00D1
Pin Mode
SPC0
(1)
MSTR
MISO
(2)
MOSI
(3)
SCK
(4)
SS
(5)
#1
Normal 0
0 Slave Out Slave In SCK In SS In
#2 1 Master In Master Out SCK Out SS I/O
#3
Bidirectional 1
0 Slave I/O GPI/O SCK In SS In
#4 1 GPI/O Master I/O SCK Out SS I/O
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)