Datasheet

Multiple Serial Interface
Port S
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Multiple Serial Interface 285
some slave devices are very simple and either accept data from the
master without returning data to the master or pass data to the master
without requiring data from the master.
15.6 Port S
In all modes, port S bits PS[7:0] can be used for either general-purpose
I/O, or with the SCI and SPI subsystems. During reset, port S pins are
configured as high-impedance inputs (DDRS is cleared).
Read anytime (inputs return pin level; outputs return pin driver input
level). Write data stored in internal latch (drives pins only if configured for
output). Writes do not change pin state when pin configured for SPI or
SCI output.
After reset all bits are configured as general-purpose inputs.
Port S shares function with the on-chip serial systems (SPI and SCI0/1).
Read or write anytime.
After reset, all general-purpose I/O are configured for input only.
0 = Configure the corresponding I/O pin for input only
1 = Configure the corresponding I/O pin for output
PORTS — Port S Data Register $00D6
Bit 7654321Bit 0
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
Pin
Function
SS
CS
SCK MOSI
MOMI
MISO
SISO
TXD1 RXD1 TXD0 RXD0
Bit 7654321Bit 0
DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0
RESET: 0 0 0 0 0 0 0 0
DDRS — Data Direction Register for Port S $00D7