Datasheet

General Description
Block Diagrams
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor General Description 29
1.6 Block Diagrams
Figure 1-1. MC68HC912D60A 112-pin QFP Block Diagram
TxCAN
DDRG
PORTG
KWG4
KWG3
KWG2
KWG1
KWG0
PG7
KWG6
KWG5
PG4
PG3
PG2
PG1
PG0
PG7
PG6
PG5
DDRH
PORTH
PH4
PH3
PH2
PH1
PH0
PH7
PH6
PH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWH7
KWH6
KWH5
PGUPD
PHUPD
PGUPD
PHUPD
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
DDRT
PORT T
60K byte flash EEPROM
2K byte RAM
PORT E
Enhanced
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
SPI
DDRS
PORT S
PORT AD1
PE1
PE2
PE4
PE5
PE6
PE3
PAD13
PAD14
PAD15
PAD16
PAD17
VDDAD
VSSAD
VRH1
VRL1
PAD10
PAD11
PAD12
RESET
EXTAL
XTAL
PW0
PW1
PW2
PW3
PWM
DDRP
PORT P
PP0
PP1
PP2
PP3
VDD ×2
VSS ×2
SCI0 (MI BUS)
RxD0
TxD0
RxD1
TxD1
SISO/MISO
MOMI/MOSI
SCK
SS
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
1K byte EEPROM
PE0
PE7
AN13
AN14
AN15
AN16
AN17
VDDAD
VSSAD
VRH1
VRL1
AN10
AN11
AN12
BKGD
ECLK
R/W
LSTRB/TAGLO
MODA/IPIPE0
MODB/IPIPE1/CGMTST
XIRQ
DBE/CAL/ECLK
capture
timer
Lite
IRQ
PCAN7
PCAN6
PCAN5
PCAN4
SCI1
integration
module
(LIM)
CPU12
Periodic interrupt
COP watchdog
Clock monitor
Single-wire
background
debug module
Breakpoints
PLL
VSSPLL
XFC
VDDPLL
CAN
RxCAN
DDRA
PORT A
DDRB
PORT B
PA4 PA3 PA2 PA1 PA0 PA7 PA6 PA5
PB4 PB3 PB2 PB1 PB0 PB7 PB6 PB5
DATA15
Multiplexed Address/Data Bus
A
D
D
R
1
5
A
D
D
R
1
4
A
D
D
R
1
3
A
D
D
R
1
2
A
D
D
R
1
1
A
D
D
R
1
0
A
D
D
R
9
A
D
D
R
8
DATA14 DATA13 DATA12
DATA11
DATA10
DATA9 DATA8
A
D
D
R
7
A
D
D
R
6
A
D
D
R
5
A
D
D
R
4
A
D
D
R
3
A
D
D
R
2
A
D
D
R
1
A
D
D
R
0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ATD1
PORT AD0
PAD03
PAD04
PAD05
PAD06
PAD07
VRH0
VRL0
PAD00
PAD01
PAD02
AN03
AN04
AN05
AN06
AN07
VDDAD
VSSAD
VRH0
VRL0
AN00
AN01
AN02
ATD0
I/O
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Wide
bus
Narrow bus
PCAN1
PCAN0
VDDX ×2
VSSX ×2
Power for internal circuitry
Power for I/O drivers
I/O
PP4
PP5
PP6
PP7
PCAN3
PCAN2