Datasheet

Freescale Interconnect Bus
Message validation
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Freescale Interconnect Bus 293
Figure 16-3. MI BUS Block Diagram
&
LOOPS
WOMS
WAKE
+
&
&
M
ILT
PE
PT
SC0CR1
10/11-bit TX shift register
H8 L07
10/11-bit RX shift register
807
TIE
TE
RIE
ILIE
RE
RWU
SBK
SC0CR2
TDRE
TC
OR
RDRF
SC0SR1
Data
recovery
RxD0
TxD0
Receive bufferR8
Transmit buffer
T8
Transmitter
control
Receiver
control
SCI interrupt request
WOMS
WOMS
MIE
PT
TE
SBK
MIE
RE
STOP START
SC0BDL SC0BDH
Rate generator
MCLK
RIE
IDLE
ILIE
RDRF
TC
TCIE
TDRE
TIE
Note: † = always reads as zero
Flag control
Internal data bus
RSRC
† † †
TCIE
NF
= not used in MI Bus mode
clock
&
SCSWAI
MDL1
MDL0
RAF
SC0SR2
MIE