Datasheet

Freescale Interconnect Bus
Technical Data MC68HC912D60A — Rev. 3.1
298 Freescale Interconnect Bus Freescale Semiconductor
PT — MI Bus TxD0 polarity
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = MI Bus transmit pin functions normally.
1 = MI Bus transmit pin will send inverted data.
Read or write anytime.
RIE — Receiver Interrupt Enable
0 = RDRF interrupt disabled.
1 = MI Bus interrupt will be requested whenever the RDRF status
flag is set.
OR does not generate an interrupt request in MI Bus mode.
TE — Transmitter Enable
0 = Transmitter disabled.
1 = MI Bus transmit logic is enabled and the TxD0 pin (Port S bit 1)
is dedicated to the transmitter.
RE — Receiver Enable
0 = Receiver disabled.
1 = Port pin dedicated to the MI Bus; the receiver is enabled by a
pull sync and is inhibited during a push field.
SBK — Send Break
0 = No action.
1 = MI transmit line is set low for 20 time slots.
When an MI Bus wire is held low for eight or more time slots an
internal circuit on any slave device connected to the bus may reset or
preset the device with default values.
Bit 7654321Bit 0
— — RIE — TE RE — SBK
RESET: 0 0 0 0 0 0 0 0
SC0CR2 — MI Bus Control Register 2 $00C3