Datasheet
General Description
Technical Data MC68HC912D60A — Rev. 3.1
30 General Description Freescale Semiconductor
Figure 1-2. MC68HC912D60A 80-pin QFP Block Diagram
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
TxCAN
DDRG
PORTG
KWG4
KWG3
KWG2
KWG1
KWG0
PG7
KWG6
KWG5
PG4
DDRH
PORTH
PH4
KWH4
KWH3
KWH2
KWH1
KWH0
KWH7
KWH6
KWH5
PGUPD(VDD)
PHUPD(VSS)
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
DDRT
PORT T
60K byte flash EEPROM
2K byte RAM
PORT E
Enhanced
SPI
DDRS
PORT S
PE1
PE2
PE4
PE5
PE6
PE3
VDDAD
VSSAD
RESET
EXTAL
XTAL
PW0
PW1
PW2
PW3
PWM
DDRP
PORT P
PP0
PP1
PP2
PP3
VDD ×2
VSS ×2
SCI0 (MI BUS)
RxD0
TxD0
RxD1
TxD1
SISO/MISO
MOMI/MOSI
SCK
SS
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
1K byte EEPROM
PE0
PE7
BKGD
capture
timer
SCI1
CPU12
Periodic interrupt
COP watchdog
Clock monitor
Single-wire
background
debug module
Breakpoints
PLL
VSSPLL
XFC
VDDPLL
CAN
RxCAN
DDRA
PORT A
DDRB
PORT B
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
DATA15
Multiplexed Address/Data Bus
A
D
D
R
1
5
A
D
D
R
1
4
A
D
D
R
1
3
A
D
D
R
1
2
A
D
D
R
1
1
A
D
D
R
1
0
A
D
D
R
9
A
D
D
R
8
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
A
D
D
R
7
A
D
D
R
6
A
D
D
R
5
A
D
D
R
4
A
D
D
R
3
A
D
D
R
2
A
D
D
R
1
A
D
D
R
0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
PORT AD0
PAD03
PAD04
PAD05
PAD06
PAD07
VRH0
VRL0
PAD00
PAD01
PAD02
AN03
AN04
AN05
AN06
AN07
VDDAD
VSSAD
VRH0
VRL0
AN00
AN01
AN02
ATD0
I/O
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Wide
bus
Narrow bus
PCAN1
PCAN0
VDDX ×2
VSSX ×2
Power for internal circuitry
Power for I/O drivers
PP4
PP5
PP6
PP7
DDRCAN
PORT CAN
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
ECLK
R/W
LSTRB/TAGLO
MODA/IPIPE0
MODB/IPIPE1/CGMTST
XIRQ
DBE/CAL/ECLK
Lite
IRQ
integration
module
(LIM)
PORT AD1
AN13
AN14
AN15
AN16
AN17
VDDAD
VSSAD
VRH1
VRL1
AN10
AN11
AN12
ATD1
Several I/O on ports G, H and CAN are unavailable externally on the 80-pin QFP package. These in-
ternal pins should either be defined as outputs or have their pull-ups/downs enabled.
Note: