Datasheet

Freescale Interconnect Bus
SCI0/MI Bus registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Freescale Interconnect Bus 301
RAF — Receiver Active Flag
0 = A character is not being received
1 = A character is being received
This register forms the 8-bit data/address word for the MI push field
and contains the 3-bit data word received as the MI pull field.
R7T7–R0T0 — Receive/Transmit Data Bits 7 to 0
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI Bus receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI Bus. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
Table 16-1. MI Bus Delay
MDL1 MDL0 Delay factor
Delay time
(1)
1. 20kHz bit rate requires 25µs (40kHz) time slots.
00 1
1.5625 µs
(2)
2. 25µs ÷ 16
01 23.125µs
10 34.6875µs
11 46.25µs
Bit 7654321Bit 0
R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
Pull field0101S1S2S31
Push fieldA2A1A0D4D3D2D1D0
RESET: ————————
SC0DRL— MI Bus Data Register Low $00C7