Datasheet

MSCAN Controller
Programmer’s Model of Message Storage
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor MSCAN Controller 325
17.12 Programmer’s Model of Message Storage
The following section details the organisation of the receive and transmit
message buffers and the associated control registers. For reasons of
programmer interface simplification the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13 byte data structure. An additional
transmit buffer priority register (TBPR) is defined for the transmit buffers.
17.12.1 Message Buffer Outline
Figure 17-11 shows the common 13 byte data structure of receive and
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 17-12. All bits of the
13 byte data structure are undefined out of reset.
Figure 17-10. Message Buffer Organization
Address
(1)
1. x is 4, 5, 6, or 7 depending on which buffer RxFG,
Tx0, Tx1, or Tx2 respectively.
Register name
01x0 Identifier register 0
01x1 Identifier register 1
01x2 Identifier register 2
01x3 Identifier register 3
01x4 Data segment register 0
01x5 Data segment register 1
01x6 Data segment register 2
01x7 Data segment register 3
01x8 Data segment register 4
01x9 Data segment register 5
01xA Data segment register 6
01xB Data segment register 7
01xC Data length register
01xD
Transmit buffer priority register
(2)
2. Not applicable for receive buffers
01xE Unused
01xF Unused