Datasheet

MSCAN Controller
Programmer’s Model of Control Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor MSCAN Controller 333
17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
SJW1, SJW0 — Synchronization Jump Width
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 17-5).
BRP5 – BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to Table 17-6.
NOTE: The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
Bit 7654321Bit 0
CBTR0 R
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
$0102 W
RESET 00000000
Table 17-5. Synchronization jump width
SJW1 SJW0 Synchronization jump width
0 0 1 Tq clock cycle
0 1 2 Tq clock cycles
1 0 3 Tq clock cycles
1 1 4 Tq clock cycles
Table 17-6. Baud rate prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Prescaler value
(P)
000000 1
000001 2
000010 3
000011 4
:::::: :
:::::: :
111111 64