Datasheet

MSCAN Controller
Programmer’s Model of Control Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor MSCAN Controller 335
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (Tq) clock cycles per bit (as
shown above).
NOTE: The CBTR1 register can only be written if the SFTRES bit in CMCR0 is set
17.13.6 msCAN12 Receiver Flag Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can only be cleared
when the condition which caused the setting is no more valid. Writing a 0
has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset clears the register.
WUPIF — Wake-up Interrupt Flag
If the msCAN12 detects bus activity while in SLEEP Mode, it sets the
WUPIF flag. If not masked, a Wake-Up interrupt is pending while this
flag is set.
0 = No wake-up activity has been observed while in SLEEP Mode.
1 = msCAN12 has detected activity on the bus and requested
wake-up.
Table 17-8. Time segment values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 TSEG22 TSEG21 TSEG20 Time segment 2
0 0 0 0 1 Tq clock cycle 0 0 0 1 Tq clock cycle
0 0 0 1 2 Tq clock cycles 0 0 1 2 Tq clock cycles
0 0 1 0 3 Tq clock cycles . . . .
0 0 1 1 4 Tq clock cycles . . . .
. . . . . 1 1 1 8 Tq clock cycles
.... .
1 1 1 1 16 Tq clock cycles
BitTime
Presc value⋅
f
CGMCANCLK
-------------------------------------------
number• of TimeQuantaÞÞ=
Bit 7654321Bit 0
CRFLG R
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF
$0104 W
RESET 0 0 000000