Datasheet

MSCAN Controller
Programmer’s Model of Control Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor MSCAN Controller 341
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event will result in a transmitter empty interrupt.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
17.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC)
IDAM1 – IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organisation (see Identifier Acceptance Filter). Table 17-8
summarizes the different settings. In Filter Closed mode no
messages are accepted such that the foreground buffer is never
reloaded.
Bit 7654321Bit 0
CIDAC R 0 0
IDAM1 IDAM0
0 IDHIT2 IDHIT1 IDHIT0
$0108 W
RESET 0 0 0 0 0 0 0 0
Table 17-9. Identifier Acceptance Mode Settings
IDAM1 IDAM0 Identifier Acceptance Mode
0 0 Two 32 bit Acceptance Filters
0 1 Four 16 bit Acceptance Filters
1 0 Eight 8 bit Acceptance Filters
1 1 Filter Closed